Memory interface device with processing capability

Claim 1

In a system having a central processor including an arithmetic logic unit (ALU), and a memory unit (MU), a memory interface device between said central processor and said memory unit comprising: (a) means coupling said central processor and said memory interface device for transmitting memory address information between said central processor and said memory interface device, (b) means coupling said memory interface device and said memory unit for transmitting memory address information between said memory interface device and said memory unit; (c) arithmetic and logic means within said memory interface device for arithmetically or logically operating on said address information, in response to control signals from other system elements, to generate an address to be transmitted to said memory unit; (d) a register file within said memory interface device, said register file including a plurality of registers; (e) means coupled to said arithmetic and logic means and to said register file for alternatively, selectively, providing an address to be transmitted to said memory unit from either a register within said register file, or a generated address from said arithmetic and logic means; (f) means coupled to said means for providing an address for transmitting a selected one of the provided addresses from said memory interface device to said memory unit, and (g) means for transmitting data between said memory interface device and said memory unit for storage or retrieval of such data in said memory unit at a location defined by the address transmitted thereto from said memory interface device.