Patent US4241413A successfully refreshed from Google Patents.
US4241413A
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Binary adder with shifting function
Assignee: CAMBRIDGE PARALLEL PROCESSING Ltd
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Filing: 1979-03-15
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Granted: 1980-12-23
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Expires: 1999-03-15
Abstract
Abstract A binary adder has a switching circuit connected to one of its inputs. When activated by a mode selection signal, the switching circuit forces two of the adder inputs to receive the same input signal. In this condition the adder acts effectively as a connector, coupling two of its inputs direct to the sum and carry outputs. The invention is useful in an array processor, for performing additions and shifting operations.
Inventors
- 👤 David J. Hunt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:23
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
219 words
An information processing arrangement comprising a sequence of processing cells, each cell containing first and second single-bit registers, a switching device having two inputs respectively connected to the two registers, a binary adder having three inputs and sum and carry outputs, means for connecting the first input to the output of the switching device, means for connecting the second input to the first register, means for connecting the third input to the carry output of the adder in the preceding cell in the sequence (if any), and means for connecting the sum output to the input of the first register, such that when the switching device in each cell selects the output from the second register, the arrangement is above to perform a parallel addition between first and second multi-bit operands contained in the first and second registers respectively, with ripple carry between adjacent cells, and when the switching device in each cell selects the output from the first register the contents of the first register in each cell can be shifted, via the carry output of the adder in that cell, into the third input of the adder in the next cell of the sequence (if any), and then via the sum output of the adder in that next cell into the first register in that next cell.
Claim 2
Dependent Claim
219 words
An information processing arrangement comprising a sequence of processing cells, each cell containing first and second single-bit registers, a switching device having two inputs respectively connected to the two registers, a binary adder having three inputs and sum and carry outputs, means for connecting the first input to the output of the switching device, means for connecting the second input to the first register, means for connecting the third input to the carry output of the adder in the preceding cell in the sequence (if any), and means for connecting the sum output to the input of the first register, such that when the switching device in each cell selects the output from the second register, the arrangement is above to perform a parallel addition between first and second multi-bit operands contained in the first and second registers respectively, with ripple carry between adjacent cells, and when the switching device in each cell selects the output from the first register the contents of the first register in each cell can be shifted, via the carry output of the adder in that cell, into the third input of the adder in the next cell of the sequence (if any), and then via the sum output of the adder in that next cell into the first register in that next cell.
Claim 3
Dependent Claim
128 words
A circuit arrangement comprising (a) a binary adder circuit having first, second and third inputs and sum and carry outputs; (b) first, second and third signal input paths; and (c) a switching device having two inputs which are connected respectively to the first and second signal input paths and having an output which is connected to the first input of the adder, (d) the second and third inputs of the adder being connected respectively to the second and third signal input paths; (e) the switching device thereby being operable to cause the first and second inputs of the adder to receive the same input signal so as to make the sum output equal to the third input and the carry output equal to the first or second input.
Claim 4
Dependent Claim
128 words
A circuit arrangement comprising (a) a binary adder circuit having first, second and third inputs and sum and carry outputs; (b) first, second and third signal input paths; and (c) a switching device having two inputs which are connected respectively to the first and second signal input paths and having an output which is connected to the first input of the adder, (d) the second and third inputs of the adder being connected respectively to the second and third signal input paths; (e) the switching device thereby being operable to cause the first and second inputs of the adder to receive the same input signal so as to make the sum output equal to the third input and the carry output equal to the first or second input.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-23 | 1984-06-23 | 1984-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-23 | 1988-06-23 | 1988-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-23 | 1992-06-23 | 1992-12-23 | $7700.00 | Window Closed / Lapsed |