Binary/bcd arithmetic logic unit

Claim 1

An arithmetic logic unit for selectively performing binary arithmetic/logic and binary-coded-decimal (BCD) arithmetic, said arithmetic logic unit comprising: a first read-only-memory with at least eight inputs for receiving binary data, binary carry information, first BCD data information, second BCD data information, and coded function information, said first read-only-memory also having at least four outputs for issuing binary result information, binary carry information, and auxiliary information; a second read-only-memory with inputs for receiving first BCD data information, auxiliary information from the first readonly-memory, binary carry information from the first read-onlymemory, and second BCD data information, said second read-onlymemory also having outputs for issuing BCD result information and decimal carry information; a first binary storage element connected between an output and an input of the first read-only-memory for storing binary carry information; a second binary storage element connected between an output of the second read-only-memory and an input of the first readonly-memory for storing decimal carry information; first logic means connected to the first and second binary storage elements and to the first read-only-memory for selectively applying binary and decimal carry information to the first read-only-memory; and second logic means for selectively enabling the first and second binary storage elements to change state.