Serial by character multifunctional modular unit

Claim 2

An arithmetic and logic unit for selectively performing arithmetic and logical operations on pairs of input signals and carry-in signals representing data in coded form under control of arithmetic and logic control signals comprising: a plurality of logical modules, one for each pair of input signals and arranged in sequential order positions from low to high order, said modules each including: Logical elements responsive to a carry-in signal and a not input signal of one input signal of said pair of input signals, to a carry-in signal and the other input signal of said pair of input signals and to said not input signal of said one input signal and said other input signal to develop a carryout signal; logical elements responsive to said other input signal and said carry-in signal and an arithmetic control signal to develop a first change bit signal; logical elements responsive to said other input signal and said not input signal of said one signal and a first logic control signal to develop a second change bit signal; logical elements responsive to a not signal of said other input signal and said one input signal and a second logic control signal to develop a third change bit signal, and means for receiving said one input signal and for passing said one input signal in response to the absence of said first, second or third change bit signals and for changing the state of said one input signal in response to the presence of said first, second or third change bit; means for applying the carryout signal from the module of one order position as a carry-in signal to the module of the adjacent higher order position; and control means for selectively applying a carry-in signal to the low-order position module and for selectively generating a plurality of control signals including said arithmetic and said first and second logic control signals.

Claim 3

The arithmetic and logic unit of claim 1 wherein said first logic control signal is an OR control signal and said second logic control signal is an AND control signal.

Claim 4

The arithmetic and logic unit of claim 1 wherein said means for receiving said one input signal includes a logical OR circuit connected to receive said first, second and third change bit signals and an exclusivE OR circuit connected to receive said one input signal and the output of said logical OR circuit.

Claim 5

The arithmetic and logic unit of claim 1 further comprising: a logical OR circuit connected to receive said first, second and third change bit signals from each module; and a logical AND circuit connected to receive output signals from said logical OR circuit and said control means to perform Test Bits On-off operations.

Claim 6

The arithmetic and logic unit of claim 1 further comprising: a six correct circuit connected to receive output signals from said modules except the low order module and to receive a carryout signal from the high-order module and a control signal from said control means and generating output signals in response to a carryout signal from said high-order module and output signals from said modules except the low-order module for changing the output signals of said modules except said low-order module; and means responsive to output signals from said six correct circuit and the outputs of said modules except said low-order module for changing the outputs of said modules except said low-order module.

Claim 7

The arithmetic and logic unit of claim 5 wherein said means responsive to signals from said six correct circuit and the outputs of said modules except said low-order module includes an exclusive OR circuit for each module except said low-order module.

Claim 8

An arithmetic and logic unit comprising: first and second registers having a plurality of bit positions for storing bits of first and second operands, said first operand being base data and said second operand being modifying data; control means selectively operable to provide a plurality of control signals including an arithmetic control signal and a carry-in signal; first logic means having a number of logic modules corresponding to the number of bit positions of said first and second registers, said modules being arranged in sequential order positions from low to high order, each logic module having a carry-in input, first and second register bit inputs and an input for receiving said arithmetic control signal and having a carryout output and a change first operand output, the modules being configured as a subtracter where the carryout output of one module is connected to the carry-in input of the module in the adjacent higher order position, the carry-in input of the low order module being connected to said control means to receive said carry-in signal and the first and second register bit inputs of each module being connected to corresponding bit positions of said first and second registers, said modules being responsive to generate a carryout signal if said carry-in signal is simultaneously present with a bit absent signal from a corresponding bit position in said first register and responsive to generate a change first operand signal if a carry-in signal is simultaneously present with the absence of a bit from the corresponding bit position of said second register or if a carry-in signal is simultaneously absent with the presence of a bit from the corresponding bit position of said second register; and second logic means connected to said first register and said first logic means and operative to change or not change the bit conditions of said first operand depending upon receiving or not receiving change first operand signals from said first logic means.

Claim 9

An arithmetic and logic unit comprising: first and second registers having a plurality of bit positions for storing bits of first and second operands, said first operand being base data and said second operand being modifying data; control means selectively operable to provide a plurality of control signals including an arithmetic control signal and a carry-in signal; first logic means having a number of logic modules corresponding to the number of bit positions of said first and second registers, said modules being arranged in sequential order positions from low to high order, each logic module having a carry-in input, first and second register bit inputs and an input for receiving said arithmetic control signal and having a carryout output and a change first operand output, the modules being configured as a subtracter where the carryout output of one module is connected to the carry-in input of the module in the adjacent higher order position, the carry-in input of the low order module being connected to said control means to receive said carry-in signal and the first and second register bit inputs of each module being connected to corresponding bit positions of said first and second registers, said modules being responsive to generate a carryout signal if said carry-in signal is simultaneously present with a bit absent signal from a corresponding bit position in said first register and responsive to generate a change first operand signal if a carry-in signal is simultaneously present with the absence of a bit from the corresponding bit position of said second register or if a carry-in signal is simultaneously absent with the presence of a bit from the corresponding bit position of said second register; and second logic means connected to said first register and said first logic means and operative to change or not change the bit conditions of said first operand depending upon receiving or not receiving change first operand signals from said first logic means.

Claim 10

The arithmetic and logic unit of claim 7 wherein said second logic means comprises: exclusive OR circuits, one for each bit position of said plurality of bit positions.

Claim 11

The arithmetic and logic unit of claim 7 further comprising: third logic means connected to said first and second registers and to said control means for receiving logic control signals and responsive to the bit conditions of said first and second operands and said logic control signals for generating control signals at one level if the bits of said first operand are to be changed And at another level if the bits of said first operand are not to be changed; and means for applying said control signals generated by said third logic means to said second logic means.