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Patent US4234934A successfully refreshed from Google Patents.
US4234934A
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Apparatus for scaling memory addresses
Assignee: Unisys Corp
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Filing: 1978-11-30
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Granted: 1980-11-18
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Expires: 1998-11-30
Abstract
Abstract Apparatus for scaling addresses received by a memory module in a modular requestor-memory system in which standard memory modules may be of a discretely variable size and utilized in a plurality of positions in an overall contiguous memory addressing scheme. In particular, this scaling apparatus enables a modular memory which is only partially populated, i.e., only able to respond to a subset of the set of all addresses available, to be located in any one of several positions representing different addressing ranges. This is accomplished without modification of the memory module itself. The memory module knows its discrete capacity, or size, by virtue of the population of the memory array storage locations (array cards) contained therein. The memory module then uses this information to scale, or strip off, the appropriate number of bits from the gross address to allow addressing of the restricted number of memory locations present in the memory module.
Inventors
- 👤 Lee T. Thorsrud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:32
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
168 words
A data processing apparatus comprising: a memory module wherein said memory module has a storage capacity depending upon a variable number of memory banks contained within said memory module; a requestor which generates a memory address to be used by said memory module wherein said memory address consists of a plurality of bits; determining means responsively coupled to said memory module for determining said variable number of memory banks contained within said memory module; stripping means responsively coupled to said requestor and said determining means for stripping from said memory address a one or more of said plurality of bits thereby producing a modified memory address wherein said modified memory address consists of a minimum number of bits sufficient to address said storage capacity of said memory module depending upon said variable number of memory banks as determined by said determining means; and means responsively coupled to said memory module and said stripping means for transferrng said modified memory address from said stripping means to said memory module.
Claim 2
Dependent Claim
168 words
A data processing apparatus comprising: a memory module wherein said memory module has a storage capacity depending upon a variable number of memory banks contained within said memory module; a requestor which generates a memory address to be used by said memory module wherein said memory address consists of a plurality of bits; determining means responsively coupled to said memory module for determining said variable number of memory banks contained within said memory module; stripping means responsively coupled to said requestor and said determining means for stripping from said memory address a one or more of said plurality of bits thereby producing a modified memory address wherein said modified memory address consists of a minimum number of bits sufficient to address said storage capacity of said memory module depending upon said variable number of memory banks as determined by said determining means; and means responsively coupled to said memory module and said stripping means for transferrng said modified memory address from said stripping means to said memory module.
Claim 3
Dependent Claim
56 words
A data processing system according to claim 1 wherein said determining means further comprises: means responsively coupled to each of said variable number of memory banks for generating a plurality of signals whereby each of said signals corresponds to the presence within said memory module of a different one of said variable number of memory banks.
Claim 4
Dependent Claim
61 words
A data processing system according to claim 2 wherein said stripping means further comprises: gating means responsively coupled to said generating means for disabling a one or more of said plurality of bits of said memory address used to uniquely address a one of said variable number of memory banks if a corresponding one of said plurality of signals is absent.
Claim 5
Dependent Claim
241 words
A memory module comprising: a variable number of memory banks wherein each of said variable number of memory banks has a fixed number of addressable locations; a memory address register responsively coupled to said variable number of memory banks for storing a modified memory address having a variable number of bits whereby said variable number of bits is a minimum number required to uniquely address a one of said fixed number of addressable locations within a one of said variable number of memory banks; means responsively coupled to said variable number of memory banks for determining said minimum number of bits required to uniquely address a one of said fixed number of addressable locations within a one of said variable number of memory banks; means for receiving a memory address from a requestor whereby said memory address contains a fixed number of bits and whereby said fixed number of bits is at least as large as said variable number of bits; means responsively coupled to said receiving means and said determining means for generating said modified memory address by stripping from said memory address a number of bits whereby said number of bits is the difference between the fixed number of bits of said memory address and said minimum number of bits determined by said determining means; and means responsively coupled to said generating means and said memory address register for loading said memory address register with said modified memory address.
Claim 6
Dependent Claim
241 words
A memory module comprising: a variable number of memory banks wherein each of said variable number of memory banks has a fixed number of addressable locations; a memory address register responsively coupled to said variable number of memory banks for storing a modified memory address having a variable number of bits whereby said variable number of bits is a minimum number required to uniquely address a one of said fixed number of addressable locations within a one of said variable number of memory banks; means responsively coupled to said variable number of memory banks for determining said minimum number of bits required to uniquely address a one of said fixed number of addressable locations within a one of said variable number of memory banks; means for receiving a memory address from a requestor whereby said memory address contains a fixed number of bits and whereby said fixed number of bits is at least as large as said variable number of bits; means responsively coupled to said receiving means and said determining means for generating said modified memory address by stripping from said memory address a number of bits whereby said number of bits is the difference between the fixed number of bits of said memory address and said minimum number of bits determined by said determining means; and means responsively coupled to said generating means and said memory address register for loading said memory address register with said modified memory address.
Claim 7
Dependent Claim
86 words
A memory module according to claim 4 wherein said determining means further comprises: means physically attached to each of said variable number of memory banks for indicating the presence of a corresponding one of said variable number of memory banks; and decoding means responsively coupled to said indicating means for decoding, from the indicating of said indicating means, said minimum number of bits required to uniquely address a one of said fixed number of addressable locations within a one of said variable number of memory banks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-18 | 1984-05-19 | 1984-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-18 | 1988-05-19 | 1988-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-18 | 1992-05-19 | 1992-11-18 | $7700.00 | Window Closed / Lapsed |