Digitally-programmed arbitrary waveform generator

Claim 2

Apparatus for generating waveforms, the apparatus comprising: variable clock means for providing pulses at a rate determined by digital data loaded into the variable clock means; amplitude output means for containing an output count; amplitude comparison register means for containing an end point count; word oriented digital memory means for storing a plurality of digital words containing instructions and data; memory address means for addressing digital words in the word oriented digital memory means in a predetermined order; instruction execution means for executing the instruction contained in each digital word addressed by the memory address means, the instructions executed by the instruction execution means including a first load instruction for loading the data from a digital word into the amplitude comparison register means, a second load instruction for loading the data from a digital word into the variable clock means, and a ramp instruction for enabling the amplitude output means to count toward the end point count contained in the amplitude comparison register means in response to pulses from the variable clock means; and comparator means for comparing the output count contained in the amplitude output means and the end point count contained in the amplitude comparison register means during a ramp operation and producing a ramp complete signal when the output count equals the end point count, the ramp complete signal indicating to the memory address means that the ramp operation is complete.

Claim 3

The apparatus of claim 1 wherein the instructions executed by the instruction execution means further include a third load operation for loading the data from a digital word into the amplitude output means.

Claim 4

The apparatus of claim 1 and further comprising: means for containing a delay count; detect means for detecting when the delay count reaches a predetermined count and providing a delay complete signal to indicate to the memory address means that a delay operation is complete; clock means for providing clock pulses; and wherein the instructions executed by the instruction execution means further include a load instruction for loading the data from a digital word into the means for containing a delay count, and a delay instruction for enabling the means for containing a delay count to count toward the predetermined count in response to clock pulses from the clock means.

Claim 5

The apparatus of claim 3 wherein the means for containing the delay count comprises the amplitude comparison register means and wherein the load instruction for loading data into the means for containing a delay count comprises the first load instruction.

Claim 6

The apparatus of claim 3 wherein the instruction execution means produces an operate command signal which enables the means for containing the delay count in response to a delay instruction.

Claim 7

The apparatus of claim 3 and further comprising: means for deriving an independent timed output from data contained in a digital word containing a delay instruction.

Claim 8

The apparatus of claim 1 and further comprising output means for deriving an output waveform from the output count of the amplitude output means.

Claim 9

The apparatus of claim 1 wherein the variable clock means comprises: clock means for providing clock signals; clock multiplier control register means for containing the data loaded in response to a second load instruction; and clock multiplier means for receiving clock signals from the clock means and providing pulses at a rate determined by the data contained in the clock multiplier control register means.

Claim 10

The apparatus of claim 8 wherein the variable clock means further comprises: clock divide and select circuitry for receiving the clock signals from the clock means and providing one of a plurality of different frequency clock signals to the clock multiplier means, the clock divide and select circuitry selecting one of the plurality of different frequency clock signals as a function of data from a digital word containing a ramp instruction.

Claim 11

The apparatus of claim 1 wherein the comparator means further provides count-up and count-down control signals to the amplitude output means to control whether the output count of the amplitude output register is incremented or decremented during a ramp operation.

Claim 12

The apparatus of claim 10 wherein the comparator means provides a count-up control signal to the amplitude output means when the output count and the end point count have the same polarity and the magnitude of the output count is less than the end point count, and wherein the comparator means provides a count-down control signal to the amplitude output means in all other cases.

Claim 13

The apparatus of claim 11 wherein the comparator means changes the polarity of the output count in the amplitude output means if the output count during a ramp operation reaches zero and does not equal the end point count.

Claim 14

The apparatus of claim 1 wherein the instruction execution means produces, in response to a load instruction, a load command signal which selects the amplitude output means, the amplitude comparison register means, or the variable clock means, and a load pulse signal which causes data from the digital word containing the load instruction to be loaded into the amplitude comparison register means, the amplitude output means, or clock means selected by the load command signal, and produces an advance signal which causes the memory address means to address the next digital word in the predetermined order after the load instruction has been executed.

Claim 15

The apparatus of claim 13 wherein the instruction execution means further produces an operate command signal which enables the amplitude output means in response to a ramp instruction.

Claim 16

The apparatus of claim 1 wherein the instructions executed by the instruction execution means further include an address jump instruction for causing the memory address means to address a preselected digital word.

Claim 17

The apparatus of claim 15 wherein the instruction execution means provides a jump command signal and a jump pulse signal to the memory address means in response to an address jump instruction, the occurrence of the jump command signal and the jump pulse signal causing the memory address means to address the preselected digital word.

Claim 18

The apparatus of claim 1 wherein the instructions executed by the instruction execution means further include a no operation instruction for causing the memory address means to advance to the next digital word in the predetermined order.

Claim 19

The apparatus of claim 17 and further comprising: means for deriving output signals from the data from a digital word containing a no operation instruction.

Claim 20

The apparatus of claim 1 wherein the instruction execution means comprises: instruction decoder means for receiving the instruction contained in the digital word addressed by the memory address means, the instruction decoder means providing load command, operate command, jump command, and sequencer trigger signals as a function of the instruction received, and register load sequencer means for providing a sequence of pulse signals, including a load pulse signal, a jump pulse signal, and an advance signal, in response to a sequencer trigger signal from the instruction decoder means.

Claim 21

The apparatus of claim 19 wherein the register load sequencer means comprises counter means which, upon receiving the sequencer trigger signal, counts through a predetermined sequence in response to clock signals from the variable clock means.

Claim 22

The apparatus of claim 1 wherein the memory address means comprises: memory address counter means for counting, in response to an advance signal from the instruction execution means and a ramp complete signal from the comparator means.

Claim 23

The apparatus of claim 21 wherein the memory address counter means further counts in response to a delay complete signal which indicates the end of a delay operation.

Claim 24

The apparatus of claim 21 wherein the memory address means further comprises: address select means for providing a preselected memory address; and wherein the instructions executed by the instruction execution means further includes an address jump instruction for loading the preselected address into the memory address counter means as the address of the next digital word to be addressed.

Claim 25

The apparatus of claim 21 wherein the memory address means further includes: memory inspection means for incrementing and decrementing the memory address counter means to inspect the contents of the word oriented digital memory.

Claim 26

The apparatus of claim 24 wherein the memory inspection means comprises: up-down jog circuitry for supplying count-up or count-down signals to the memory address counter means; address display means for displaying the address contained in the memory address counter means; and data display means for displaying the data contained in an addressed word of the word oriented digital memory means.

Claim 27

The apparatus of claim 1 and further comprising: second variable clock means for providing pulses at a rate determined by digital data loaded into the second variable clock means; second amplitude output means for containing a second output count; and wherein the instructions executed by the instruction execution means include a load instruction for loading the data from a digital word into the second variable clock means and a ramp instruction for enabling the second amplitude output means to count in response to pulses from the second variable clock means.

Claim 28

Apparatus for generating waveforms in the form of slope segments, amplitude plateaus, and amplitude jumps, the apparatus comprising: variable clock means for providing pulses at a rate determined by a pulse rate count; amplitude output means for containing an output count; amplitude comparison register means for containing an end point count; means for containing a delay count; memory means for storing a plurality of digital words containing instructions and data, the digital words including: a word including a new output count and an instruction to load the amplitude output means; a word containing an end point count and instruction to load the amplitude comparison register means; a word containing a pulse rate count and an instruction to load the variable clock means; a word containing a delay count and an instruction to load the means for containing a delay count; a word containing a ramp instruction; and a word containing a delay instruction; memory address means for addressing digital words in the memory means in a predetermined order; instruction execution means for executing the instructions contained in the digital words addressed by the memory address means; comparator means for comparing the output count contained in the amplitude output means and the end point count contained in the amplitude comparison regisrer means during a ramp operation and providing a ramp complete signal when the output count equals the input count, the ramp complete signal indicating to the memory address means that the ramp operation is complete; and detect means for detecting when the delay count reaches a predetermined count during a delay operation and providing a delay complete signal to indicate to the memory address means that a delay operation is complete.

Claim 29

Apparatus for generating waveforms in the form of slope segments, amplitude plateaus, and amplitude jumps, the apparatus comprising: variable clock means for providing pulses at a rate determined by a pulse rate count; amplitude output means for containing an output count; amplitude comparison register means for containing an end point count; means for containing a delay count; memory means for storing a plurality of digital words containing instructions and data, the digital words including: a word including a new output count and an instruction to load the amplitude output means; a word containing an end point count and instruction to load the amplitude comparison register means; a word containing a pulse rate count and an instruction to load the variable clock means; a word containing a delay count and an instruction to load the means for containing a delay count; a word containing a ramp instruction; and a word containing a delay instruction; memory address means for addressing digital words in the memory means in a predetermined order; instruction execution means for executing the instructions contained in the digital words addressed by the memory address means; comparator means for comparing the output count contained in the amplitude output means and the end point count contained in the amplitude comparison regisrer means during a ramp operation and providing a ramp complete signal when the output count equals the input count, the ramp complete signal indicating to the memory address means that the ramp operation is complete; and detect means for detecting when the delay count reaches a predetermined count during a delay operation and providing a delay complete signal to indicate to the memory address means that a delay operation is complete.

Claim 30

The apparatus of claim 27 wherein the means for containing a delay count comprises the amplitude comparison register means.

Claim 31

The apparatus of claim 28 wherein the instruction execution means enables the amplitude output means to count toward the end point count in response to pulses from the variable clock means during a ramp operation, and enables the amplitude comparison register means to count toward the predetermined count in response to pulses from the variable clock means during a delay operation.

Claim 32

Apparatus for generating first and second waveforms, the apparatus comprising: first variable clock means for providing first pulses at a first rate determined by a first pulse rate count; second variable clock means for providing second pulses at a second rate determined by a second pulse rate count; first amplitude output means for containing a first output count; second amplitude output means for containing a first output count; first amplitude comparison register means for containing a first end point count; second amplitude comparison register means for containing a second end point count; memory means for storing a plurality of digital words containing instructions and data, the digital words including: a word containing a first end point count and an instruction to load the first amplitude comparison register means; a word containing a second end point count and an instruction to load the second amplitude comparison register means; a word containing a first pulse rate count and an instruction to load the first variable clock means; a word containing a second pulse rate count and an instruction to load the second variable clock means; a word containing a ramp instruction; memory address means for addressing digital words in the memory means in a predetermined order; instruction execution means for executing the instructions contained in the digital words addressed by the memory address means; first comparator means for comparing the first output count contained in the first amplitude output means and the first end point count contained in the first amplitude comparison register means during a ramp operation and providing a ramp complete signal when the output count equals the input count, the ramp complete signal indicating to the memory address means that the ramp operation is complete; and second comparator means for comparing the second output count contained in the second amplitude output means and the second end point count contained in the second amplitude comparison register means during a ramp operation.

Claim 33

Apparatus for generating first and second waveforms, the apparatus comprising: first variable clock means for providing first pulses at a first rate determined by a first pulse rate count; second variable clock means for providing second pulses at a second rate determined by a second pulse rate count; first amplitude output means for containing a first output count; second amplitude output means for containing a first output count; first amplitude comparison register means for containing a first end point count; second amplitude comparison register means for containing a second end point count; memory means for storing a plurality of digital words containing instructions and data, the digital words including: a word containing a first end point count and an instruction to load the first amplitude comparison register means; a word containing a second end point count and an instruction to load the second amplitude comparison register means; a word containing a first pulse rate count and an instruction to load the first variable clock means; a word containing a second pulse rate count and an instruction to load the second variable clock means; a word containing a ramp instruction; memory address means for addressing digital words in the memory means in a predetermined order; instruction execution means for executing the instructions contained in the digital words addressed by the memory address means; first comparator means for comparing the first output count contained in the first amplitude output means and the first end point count contained in the first amplitude comparison register means during a ramp operation and providing a ramp complete signal when the output count equals the input count, the ramp complete signal indicating to the memory address means that the ramp operation is complete; and second comparator means for comparing the second output count contained in the second amplitude output means and the second end point count contained in the second amplitude comparison register means during a ramp operation.