US3716705A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pattern generator and method
Assignee: Individual
•
Filing: 1970-08-18
•
Granted: 1973-02-13
•
Expires: 1990-08-18
Abstract
Abstract Pattern generator and method for generating functional representations of line segments consisting of discrete increments. Standard logic elements are utilized in tree networks which successively combine length and direction input data of different orders of magnitude to produce line segment representations of increasing orders of magnitude. The tree networks are constructed in stages which can readily be cascaded to increase the numbers of increments and line segments which can be generated.
Inventors
- 👤 R Newell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:10
CPC Classifications
G; G06; G06K; G06K15/00; G06K15/22; G09; G09G; G09G1/00; G09G1/06; G09G1/08; G09G1/10
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
284 words
In a controller for generating line segment signal patterns representing vectors with each pattern being characterized by at least two parameters including length and direction, input means for receiving input information in the form of digitally coded signals, memory means for memorizing the direction parameter of at least one line segment signal pattern previously generated, means for recognizing if said digitally coded signals contain change instructions for said memorized direction parameter, the recognizing means also including means for updating said memorized parameter in response to any change instruction, said parameter being incremented or decremented according to a predetermined base number system, said updated memorized parameter having a format of a plurality of successive orders of the radix of said number system, the improvement comprising generator means including a plurality of logic means respectively associated with and responsive to said plurality of orders of said radix, the logic means associated with said lowest order radix being responsive to such order portion of said updated parameter for generating two output signal patterns representing line segments having a number of increments in accordance with the value of said radix raised to said lowest order, said two signal patterns being adjacent each other, the logic means associated with the next to lowest order radix being responsive to such order portion of said updated parameter and to said two output signal patterns of said lowest order logic means for generating at least one output signal pattern representing a line segment having a number of increments in accordance with the value of said radix raised to said next to lowest order radix, such pattern being a composite of said two output signal patterns as determined by said second order format.
Claim 2
Dependent Claim
284 words
In a controller for generating line segment signal patterns representing vectors with each pattern being characterized by at least two parameters including length and direction, input means for receiving input information in the form of digitally coded signals, memory means for memorizing the direction parameter of at least one line segment signal pattern previously generated, means for recognizing if said digitally coded signals contain change instructions for said memorized direction parameter, the recognizing means also including means for updating said memorized parameter in response to any change instruction, said parameter being incremented or decremented according to a predetermined base number system, said updated memorized parameter having a format of a plurality of successive orders of the radix of said number system, the improvement comprising generator means including a plurality of logic means respectively associated with and responsive to said plurality of orders of said radix, the logic means associated with said lowest order radix being responsive to such order portion of said updated parameter for generating two output signal patterns representing line segments having a number of increments in accordance with the value of said radix raised to said lowest order, said two signal patterns being adjacent each other, the logic means associated with the next to lowest order radix being responsive to such order portion of said updated parameter and to said two output signal patterns of said lowest order logic means for generating at least one output signal pattern representing a line segment having a number of increments in accordance with the value of said radix raised to said next to lowest order radix, such pattern being a composite of said two output signal patterns as determined by said second order format.
Claim 3
Dependent Claim
284 words
In a controller for generating line segment signal patterns representing vectors with each pattern being characterized by at least two parameters including length and direction, input means for receiving input information in the form of digitally coded signals, memory means for memorizing the direction parameter of at least one line segment signal pattern previously generated, means for recognizing if said digitally coded signals contain change instructions for said memorized direction parameter, the recognizing means also including means for updating said memorized parameter in response to any change instruction, said parameter being incremented or decremented according to a predetermined base number system, said updated memorized parameter having a format of a plurality of successive orders of the radix of said number system, the improvement comprising generator means including a plurality of logic means respectively associated with and responsive to said plurality of orders of said radix, the logic means associated with said lowest order radix being responsive to such order portion of said updated parameter for generating two output signal patterns representing line segments having a number of increments in accordance with the value of said radix raised to said lowest order, said two signal patterns being adjacent each other, the logic means associated with the next to lowest order radix being responsive to such order portion of said updated parameter and to said two output signal patterns of said lowest order logic means for generating at least one output signal pattern representing a line segment having a number of increments in accordance with the value of said radix raised to said next to lowest order radix, such pattern being a composite of said two output signal patterns as determined by said second order format.
Claim 4
Dependent Claim
284 words
In a controller for generating line segment signal patterns representing vectors with each pattern being characterized by at least two parameters including length and direction, input means for receiving input information in the form of digitally coded signals, memory means for memorizing the direction parameter of at least one line segment signal pattern previously generated, means for recognizing if said digitally coded signals contain change instructions for said memorized direction parameter, the recognizing means also including means for updating said memorized parameter in response to any change instruction, said parameter being incremented or decremented according to a predetermined base number system, said updated memorized parameter having a format of a plurality of successive orders of the radix of said number system, the improvement comprising generator means including a plurality of logic means respectively associated with and responsive to said plurality of orders of said radix, the logic means associated with said lowest order radix being responsive to such order portion of said updated parameter for generating two output signal patterns representing line segments having a number of increments in accordance with the value of said radix raised to said lowest order, said two signal patterns being adjacent each other, the logic means associated with the next to lowest order radix being responsive to such order portion of said updated parameter and to said two output signal patterns of said lowest order logic means for generating at least one output signal pattern representing a line segment having a number of increments in accordance with the value of said radix raised to said next to lowest order radix, such pattern being a composite of said two output signal patterns as determined by said second order format.
Claim 5
Dependent Claim
60 words
A controller as in claim 1 where said memory means also includes a length memory and said recognizing means also updates said length memory said updated length memory having a format similar to said direction memory, the respective order radices of said length memory providing information respectively to said plurality of logic means for generating said composite output signal pattern.
Claim 6
Dependent Claim
60 words
A controller as in claim 1 where said signal patterns are identical for each of a predetermined plurality of sectors of a circle and where said pattern generator includes steering network means coupled to said memory means and responsive to said updated memorized parameter for steering said composite output signal pattern to a sector as determined by said updated parameter.
Claim 7
Dependent Claim
181 words
In a pattern generator for generating output signal patterns representing lIne segments consisting of a predetermined number of discrete increments, means for providing data representing the length and direction of the segments said means including data lines arranged in groups carrying the data in successive orders of magnitude in a predetermined number system, a first stage of logic means connected to the group of data lines carrying the lowest order length and direction data, said first stage combining said lowest order data to produce a first order functional representation of a line segment and at least one additional stage of logic means, each additional stage being connected to the preceding stage and to the data lines carrying the next order length and direction data, each additional stage combining the functional representation from the preceding stage together with the next order length and direction data to produce the next higher order functional representation of the line segment in such manner that each lower order functional representation can form part of at least two different higher order functional representations of a line segment.
Claim 8
Dependent Claim
181 words
In a pattern generator for generating output signal patterns representing lIne segments consisting of a predetermined number of discrete increments, means for providing data representing the length and direction of the segments said means including data lines arranged in groups carrying the data in successive orders of magnitude in a predetermined number system, a first stage of logic means connected to the group of data lines carrying the lowest order length and direction data, said first stage combining said lowest order data to produce a first order functional representation of a line segment and at least one additional stage of logic means, each additional stage being connected to the preceding stage and to the data lines carrying the next order length and direction data, each additional stage combining the functional representation from the preceding stage together with the next order length and direction data to produce the next higher order functional representation of the line segment in such manner that each lower order functional representation can form part of at least two different higher order functional representations of a line segment.
Claim 9
Dependent Claim
44 words
A pattern generator as in claim 4 wherein the number of stages is equal to the exponential power to which the base of the number system utilized in arranging the data must be raised to equal the number of increments in each line segment.
Claim 10
Dependent Claim
16 words
A pattern generator as in claim 4 wherein the number system utilized is a ternary system.
Claim 11
Dependent Claim
38 words
A pattern generator as in claim 4 further including steering means for combining the highest order functional representation with directional data representing the orientation of the line segment to provide an output signal pattern representing the line segment.
Claim 12
Dependent Claim
53 words
A pattern generator as in claim 4 wherein each of said stages of logic means includes a plurality of logic elements connected in a tree network to provide a unidirectional flow of data, said tree network allowing a plurality of said stages to be serially cascaded to expand the capacity of said generator.
Claim 13
Dependent Claim
14 words
A pattern generator as in claim 8 wherein said logic elements are NOR gates.
Claim 14
Dependent Claim
95 words
In a method for generating line segment signal patterns from data in the form of length and direction parameters, the steps of arranging the length parameters and the direction parameters in a format according to increasing orders of magnitude, combining the length parameter and the direction of the lowest order of magnitude to form a lowest order functional representation of a line segment, and combining said lowest order functional representation with the length parameter and the direction parameter of the next higher order to form a next higher order functional representation of the line segment.
Claim 15
Dependent Claim
95 words
In a method for generating line segment signal patterns from data in the form of length and direction parameters, the steps of arranging the length parameters and the direction parameters in a format according to increasing orders of magnitude, combining the length parameter and the direction of the lowest order of magnitude to form a lowest order functional representation of a line segment, and combining said lowest order functional representation with the length parameter and the direction parameter of the next higher order to form a next higher order functional representation of the line segment.
Claim 16
Dependent Claim
31 words
A method as in claim 10 together with the additional step of combining length and direction parameters of a still higher order of magnitude with said next higher order functional representation.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-13 | 1976-08-14 | 1977-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-13 | 1980-08-14 | 1981-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-13 | 1984-08-14 | 1985-02-13 | $7700.00 | Window Closed / Lapsed |