Patent US4211941A successfully refreshed from Google Patents.
US4211941A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuitry including low-leakage capacitance
Assignee: RCA Corp
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Filing: 1978-08-03
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Granted: 1980-07-08
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Expires: 1998-08-03
Abstract
Abstract An integrated-circuit MOS capacitor has a first doped semiconductive region forming one of its plates. This first semiconductor region is electrically isolated from the semiconductor substrate by a second doped semiconductor region, which is of opposite conductivity type to and intervenes between the substrate and the first semiconductive region. The present invention resides in the combination of such an MOS capacitor and a circuit for maintaining the potential in the second semiconductor region of the MOS capacitor structure substantially the same as that appearing on the first semiconductor region for minimizing leakage current flow between them. This circuit also provides the leakage current flowing between the second semiconductor region and the substrate, so the leakage current need not flow from the first semiconductor region.
Inventors
- 👤 Otto H. Schade, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:03
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/08; H03F1/083; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D84/00; H10D84/201; H10D84/204; H10D84/212
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
216 words
An integrated circuit including a low-leakage capacitance comprising: a semiconductor substrate of a first conductivity type material; a first supply terminal for receiving a reference potential; means providing ohmic contact between said semiconductor substrate and said first terminal; an MOS parallel plate capacitor having as its first plate a first electrode, having as its second plate a first semiconductor region of said first conductivity type with an ohmically contacting second electrode, and having a dielectric layer between its first and second plates, and having a second semiconductor region of a second conductivity type complementary to said first conductivity type, which second semiconductor region having an ohmically contacting third electrode and forming first and second isolating pn junctions, respectively, with said first semiconductor region and said substrate; means connected to the first and second electrodes of said MOS capacitor for utilizing the capacitance therebetween; means for causing a determinable potential, different from said reference potential, at said second electrode; means for applying to the third electrode of said MOS capacitor a similar valued potential to said determinable potential thereby to eliminate a potential across said first pn junction and forestall appreciable leakage current through said first junction which means includes, means exclusive of said first pn junction for supplying leakage current flow across said second pn junction.
Claim 2
Dependent Claim
216 words
An integrated circuit including a low-leakage capacitance comprising: a semiconductor substrate of a first conductivity type material; a first supply terminal for receiving a reference potential; means providing ohmic contact between said semiconductor substrate and said first terminal; an MOS parallel plate capacitor having as its first plate a first electrode, having as its second plate a first semiconductor region of said first conductivity type with an ohmically contacting second electrode, and having a dielectric layer between its first and second plates, and having a second semiconductor region of a second conductivity type complementary to said first conductivity type, which second semiconductor region having an ohmically contacting third electrode and forming first and second isolating pn junctions, respectively, with said first semiconductor region and said substrate; means connected to the first and second electrodes of said MOS capacitor for utilizing the capacitance therebetween; means for causing a determinable potential, different from said reference potential, at said second electrode; means for applying to the third electrode of said MOS capacitor a similar valued potential to said determinable potential thereby to eliminate a potential across said first pn junction and forestall appreciable leakage current through said first junction which means includes, means exclusive of said first pn junction for supplying leakage current flow across said second pn junction.
Claim 3
Dependent Claim
132 words
An integrated circuit as set forth in claim 1 wherein said utilization means includes: a first transistor disposed in said substrate having base and collector electrodes to which the second and first electrodes of said MOS capacitor are respectively connected and having an emitter electrode; means for connecting the emitter electrode of said first transistor to said reference potential without substantial intervening impedance; means for connecting the collector electrode of said first transistor to receive an operating current; means for applying a varying current to the base electrode of said first transistor for causing said transistor to conductor between its collector and emitter electrodes and for causing the determinable potential at said second electrode to be substantially equal to the offset potential appearing between the base and emitter of said first transistor.
Claim 4
Dependent Claim
173 words
An integrated circuit as set forth in claim 2 wherein the means for applying to the third electrode of said MOS capacitor a similar-valued potential to said determinable potential and said means for supplying leakage current flow across said second pn junction together comprise; a second transistor of the same conductivity type as said first transistor, disposed in said substrate and having base and collector and emitter electrodes, said second transistor being arranged to be operated at substantially the same temperature as said first transistor; means connecting the emitter electrode of said second transistor to said reference potential without substantial intervening impedance; means for applying a current of the same polarity as said operating current to the collector electrode of said second transistor; direct coupled feedback connection from the collector to base electrodes of said second transistor for adjusting the base potential of said second transistor to condition it to conduct said applied current; and means for applying the base potential of said second transistor to the third electrode of said MOS capacitor.
References Cited (Backward Citations)
US3654498A
Cited
US3879640A
Cited
US4039857A
Cited
US4161742A
Cited
US4034395A
Cited
US4164668A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-07-08 | 1984-01-07 | 1984-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-07-08 | 1988-01-07 | 1988-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-07-08 | 1992-01-07 | 1992-07-08 | $7700.00 | Window Closed / Lapsed |