Patent US4199385A successfully refreshed from Google Patents.
US4199385A
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Method of making an optically isolated monolithic light emitting diode array utilizing epitaxial deposition of graded layers and selective diffusion
Assignee: International Business Machines Corp
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Filing: 1979-03-05
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Granted: 1980-04-22
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Expires: 1999-03-05
Abstract
Abstract Monolithic light emitting diode arrays may be fabricated by using a two layer binary semiconductor substrate wafer providing a gradient of ingredient concentration in one portion of the wafer and forming p-n junctions to a desired depth in the graded concentrated wafer and selectively removing portions of the opposite side of the wafer adjacent to said p-n junctions in order to permit light of varying colors to escape and to provide optical isolation. Metallurgical pads are provided to each of the p-n junctions for solder reflow type connections.
Inventors
- 👤 Roland Y. Hung
- 👤 Kwang K. Shih
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:35
CPC Classifications
H; H10; H10H; H10H29/00; H10H29/10; H10H29/14; H10H20/00; H10H20/80; H10H20/81; H10H20/811; H10H20/822; H10H20/824
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
106 words
The process of forming an integrated light emitting diode array comprising in combination the steps of; providing a substrate of optically isolating semiconductor material; growing an epitaxial region of a compound semiconductor material selected from the group consisting of AB 1-x C x and AxB 1-x C, said material having a vertical variation in the x value of the concentration of ingredients and decreasing in the direction of the surface of said region; forming a plurality of p-n junctions to selected depths in said epitaxial region. removing portions of said substrate in registration with said p-n junctions; and providing electrical contact across each said p-n junction.
Claim 2
Dependent Claim
106 words
The process of forming an integrated light emitting diode array comprising in combination the steps of; providing a substrate of optically isolating semiconductor material; growing an epitaxial region of a compound semiconductor material selected from the group consisting of AB 1-x C x and AxB 1-x C, said material having a vertical variation in the x value of the concentration of ingredients and decreasing in the direction of the surface of said region; forming a plurality of p-n junctions to selected depths in said epitaxial region. removing portions of said substrate in registration with said p-n junctions; and providing electrical contact across each said p-n junction.
Claim 3
Dependent Claim
29 words
The process of claim 1 including the further step of applying an optically isolating layer with openings formed over said substrate region in registration with each said p-n junction.
Claim 4
Dependent Claim
20 words
The process of claim 1 wherein said substrate is GaAs and said graded region is Al x Ga 1-x As.
Claim 5
Dependent Claim
20 words
The process of claim 1 wherein said substrate is GaP and said graded region is GaAs 1-x P x .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-22 | 1983-10-22 | 1984-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-22 | 1987-10-22 | 1988-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-22 | 1991-10-22 | 1992-04-22 | $7700.00 | Window Closed / Lapsed |