US4197631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor components
Assignee: BBC Brown Boveri AG Switzerland
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Filing: 1977-12-06
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Granted: 1980-04-15
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Expires: 1997-12-06
Abstract
Abstract A method of fabricating semiconductor components having electrodes and terminals. The method includes preparing an undivided semiconductor wafer having at least one pn-junction; etching a grid pattern of grooves into at least one side of the undivided wafer, thereby forming mesas with concave side surfaces and elevations with upper surfaces bounded by closed rounded curves; coating the exposed lateral surfaces of the etched mesas with a passivating layer; metallizing the upper surfaces of these elevations, thereby providing ohmic contacts for the undivided semiconductor wafer; and breaking the undivided semiconductor wafer into individual semiconductor chips along the lines of the etched grooves.
Inventors
- 👤 Eckhard Meyer
- 👤 Gunter Berndes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:23
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/01; H10W72/0198; H10D; H10D12/00; H10D12/01; H10D12/031; H10D18/00; H10D18/01; H10D18/031; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/104; H10D62/117; H10D62/80; H10D62/83; H10D62/832; H10D62/8325; H10P; H10P54/00; H10W72/30; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
184 words
A method of fabricating semiconductor high reverse voltage thyristors having electrodes and terminals, comprising the steps of: preparing an undivided semiconductor wafer having opposed sides and at least one pn-junction formed between said opposed sides, etching matching grid patterns of grooves into the opposed sides of said undivided wafer, said etching forming on said opposed sides matching mesas with concave side surfaces and opposed elevations with upper surfaces bounded by closed rounded curves, coating the exposed lateral surfaces of said mesas with a passivating layer, metallizing said upper surfaces of the said elevations, thereby providing ohmic contacts for said undivided semiconductor wafer, tinning with solder at least one side of a plurality of disks composed of electrically and thermally conducting material, locating the tinned disks with the tinned side thereof in contact wtih selected of the metallized upper surfaces of said elevations on the opposed sides of said undivided wafer, soldering simultaneously each of said disks to said selected elevations on opposed sides of said undivided wafer, and breaking said undivided semiconductor wafer into individual semiconductor chips along the lines of said etched grooves.
Claim 2
Independent Claim
184 words
A method of fabricating semiconductor high reverse voltage thyristors having electrodes and terminals, comprising the steps of: preparing an undivided semiconductor wafer having opposed sides and at least one pn-junction formed between said opposed sides, etching matching grid patterns of grooves into the opposed sides of said undivided wafer, said etching forming on said opposed sides matching mesas with concave side surfaces and opposed elevations with upper surfaces bounded by closed rounded curves, coating the exposed lateral surfaces of said mesas with a passivating layer, metallizing said upper surfaces of the said elevations, thereby providing ohmic contacts for said undivided semiconductor wafer, tinning with solder at least one side of a plurality of disks composed of electrically and thermally conducting material, locating the tinned disks with the tinned side thereof in contact wtih selected of the metallized upper surfaces of said elevations on the opposed sides of said undivided wafer, soldering simultaneously each of said disks to said selected elevations on opposed sides of said undivided wafer, and breaking said undivided semiconductor wafer into individual semiconductor chips along the lines of said etched grooves.
Claim 3
Dependent Claim
27 words
A method of fabricating semiconductor components according to claim 1 wherein said etching step further comprises: forming elevations with circular upper surfaces on said undivided semiconductor wafer.
Claim 4
Dependent Claim
63 words
A method for fabricating semiconductor components according to claim 1 wherein said locating and soldering steps further comprise: placing said disks on a template matching said grid pattern of said undivided wafer, laying one side of said wafer on said template, and soldering simultaneously said disks to said upper surfaces of said elevations in a plane parallel to the plane of said wafer.
Claim 5
Dependent Claim
145 words
A method of fabricating semiconductor devices according to claim 1, wherein said tinning, locating and soldering steps further comprise: tinning with solder at least one side of a plurality of first disks composed of electrically thermally conductive material, placing said disks on a first template matching said grid pattern on one side of said undivided wafer, tinning with solder at least one side of a plurality of perforated second disks composed of electrically and thermally conductive material, laying said one side of said wafer on said first template, laying a second template matching said grid pattern on the other side of said wafer, placing said perforated second disks on said second template, and soldering simultaneously said disks and said perforated disks, respectively placed in said first and second templates to said upper surfaces of said elevations in planes parallel to the plane of said wafer.
Claim 6
Dependent Claim
37 words
A method for fabricating semiconductor components according to claim 4 wherein: said first disks and said perforated second disks comprise molybdenum disks, and said soldering step uses a solder from the group consisting of lead-silver or lead-tin.
Claim 7
Dependent Claim
91 words
A method for fabricating semiconductor components according to claim 4 comprising the additional steps of: measuring the inverse voltage rating of each semiconductor chip formed by said etched grooves before placing said first disks and said perforated second disks in said first and second templates respectively, detecting the locations of defective semiconductor chips, storing in a memory said locations of said defective semiconductor chips, and placing said first disks and said perforated second disks only in those locations of said first and second templates respectively which correspond to non-defective semi-conductor chips.
Claim 8
Dependent Claim
30 words
A method of fabricating semiconductor components according to claim 3 wherein said soldering step further comprises: soldering control leads for said semiconductor components simultaneously with said soldering of said disks.
Claim 9
Dependent Claim
59 words
A method of fabricating semiconductor components according to claim 4 wherein said step of breaking said semiconductor wafer along said grooves is followed by the additional step of: embedding the individual semiconductor chips formed by the breaking in plastic such that said disks on said one side and said perforated disks on said other side protrude through said plastic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-15 | 1983-10-15 | 1984-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-15 | 1987-10-15 | 1988-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-15 | 1991-10-15 | 1992-04-15 | $7700.00 | Window Closed / Lapsed |