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US3795045A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating semiconductor devices to facilitate early electrical testing

Assignee: Silec Semi Conducteurs SA
•
Filing: 1971-02-11
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Granted: 1974-03-05
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Expires: 1991-02-11
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Abstract

Abstract A method of fabricating semiconductor devices to facilitate electrical testing at an early stage and before final assembly to heat sinks and the like. A metallic layer is deposited over one surface of a semiconductor wafer having a previously formed internal junction or junctions. The other surface of the wafer is then coated with a chemically impervious protective layer in a grid pattern, and the exposed semiconductive material is chemically cut down to the metallic layer to form islands of junction devices separated by grooves. The grooves are next filled with a protective substance to cover the exposed junctions and the devices are electrically tested. The devices are then separated by mechanically cutting through the grooves and metallic layer, and the acceptable ones are mounted on their final supports or heat sinks.

Inventors

  • 👤 G Dumas

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 09:23
CPC Classifications
H; H10; H10W; H10W72/00; H10P; H10P52/00; H10W72/30; H10W74/00; H10W74/10; H10W74/131; H10W72/071; H10W72/073; H10W72/07331; H10W72/07336

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 193 words
A method of fabricating finished semi-conductive devices from a semiconductor wafer having an internal junction, comprising: a. depositing a metallic support layer on one surface of the wafer, b. selectively coating one opposite surface of the wafer through a mask in a waffle pattern with a material impervious to cutting and etching chemicals subsequently to be employed, said coating being applied over the areas from which semiconductive devices are to be fabricated, c. chemically cutting grooves through the thickness of the wafer and down to the metallic layer in those areas that were not selectively coated, thereby forming islands of semiconductor devices supported on the metallic layer and separated by intersecting lines of grooves, d. filling the grooves between the islands with a protective substance to cover the exposed junctions in the sides of the devices by placing a mask having holes opposite each groove line intersection over the semiconductor device and applying pressure to the protective substance to force it through the holes into the grooves, and e. mechanically cutting down the middle of the grooves through the protective substance and the metallic layer to separate the semiconductive devices from each other.
Claim 2
Independent Claim 193 words
A method of fabricating finished semi-conductive devices from a semiconductor wafer having an internal junction, comprising: a. depositing a metallic support layer on one surface of the wafer, b. selectively coating one opposite surface of the wafer through a mask in a waffle pattern with a material impervious to cutting and etching chemicals subsequently to be employed, said coating being applied over the areas from which semiconductive devices are to be fabricated, c. chemically cutting grooves through the thickness of the wafer and down to the metallic layer in those areas that were not selectively coated, thereby forming islands of semiconductor devices supported on the metallic layer and separated by intersecting lines of grooves, d. filling the grooves between the islands with a protective substance to cover the exposed junctions in the sides of the devices by placing a mask having holes opposite each groove line intersection over the semiconductor device and applying pressure to the protective substance to force it through the holes into the grooves, and e. mechanically cutting down the middle of the grooves through the protective substance and the metallic layer to separate the semiconductive devices from each other.
Claim 3
Dependent Claim 50 words
A method as defined in claim 1, further including the step of electrically testing each semiconductor device while it is laterally insulated from adjacent devices by the protective substance applied in subparagraph (d) and before it is separated from the adjacent devices by the mechanical cutting recited in sub-paragraph e).
Claim 4
Dependent Claim 39 words
A method as defined in claim 2, wherein the testing is implemented by applying a first test electrode to the metallic support layer and then successively applying a second test electrode to the top part of each semiconductor device.

References Cited (Backward Citations)

US2784479A Cited
US3178796A Cited
US3158788A Cited
US3383255A Cited
US3432919A Cited
US3629023A Cited
US3579815A Cited
US3706129A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-03-04 1977-09-03 1978-03-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-03-04 1981-09-03 1982-03-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-03-04 1985-09-03 1986-03-05 $7700.00 Window Closed / Lapsed

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