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Patent US4196360A successfully refreshed from Google Patents.
US4196360A
Expired / Lapsed
US
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Interface driver circuit
Assignee: General Electric Co
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Filing: 1978-01-24
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Granted: 1980-04-01
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Expires: 1998-01-24
Abstract
Abstract An interface driver circuit, for use in a programmable energy load controller system, comprises a pair of optically-coupled input sections, respectively receiving data and a special signal of digital nature and a first voltage polarity. A buffer amplifier section is coupled to the data input circuit for driving a twisted-wire transmission line, coupled to the paralleled inputs of a plurality of receivers, with logic signals alternating essentially between ground potential and the first voltage at the first polarity; a second amplifier section is enabled by the special signal input section and impresses a voltage of the remaining polarity across the interface driver circuit output when commanded at the special signal input, regardless of the state of the data signal at the first input.
Inventors
- 👤 Edward B. Miller
- 👤 Charles W. Eichelberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:51
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K19/00; H03K19/0175; H03K19/017545; H03K19/017572; H03K5/01; H03K5/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
137 words
An interface driver circuit for transmitting signals via a transmission medium, comprising: first input means for receiving a first logic signal of a first polarity; second means for receiving a second logic signal of said first polarity; an output; third means coupled between said first means and said output for driving said medium with the data of said first logic signal between first and second values of a voltage of said first polarity, said second means being coupled to said third means to cause said third means to be disabled whenever said second logic signal is received at said second means; and fourth means coupled between said second means and said output for driving said medium with the data of said second logic signal between said first and second values of a voltage of the remaining polarity.
Claim 2
Dependent Claim
137 words
An interface driver circuit for transmitting signals via a transmission medium, comprising: first input means for receiving a first logic signal of a first polarity; second means for receiving a second logic signal of said first polarity; an output; third means coupled between said first means and said output for driving said medium with the data of said first logic signal between first and second values of a voltage of said first polarity, said second means being coupled to said third means to cause said third means to be disabled whenever said second logic signal is received at said second means; and fourth means coupled between said second means and said output for driving said medium with the data of said second logic signal between said first and second values of a voltage of the remaining polarity.
Claim 3
Dependent Claim
20 words
The circuit as set forth in claim 1, wherein each of said first and second means include an optoelectronic isolator.
Claim 4
Dependent Claim
210 words
An interface driver circuit for transmitting signals via a transmission medium, comprising: first input means for receiving a first logic signal of a first polarity; second means for receiving a second logic signal of said first polarity; an output; third means including first and second potential sources of differing magnitudes and of said first polarity; first semiconductor switch means coupled between said first potential source and said output; second semiconductor switch means coupled between said second potential source and said output; and means for causing said first and second semiconductor switch means to respectively couple the associated one of said first and second sources of potential to said output dependent upon the state of the logic signal received at said first means, for driving said medium with the data of said first logic signal between first and second values of a voltage of said first polarity; said second means being coupled to said third means to cause said third means to be disabled whenever said second logic signal is received at said second means; and fourth means coupled between said second means and said output for driving said medium with the data of said second logic signal between said first and second values of a voltage of the remaining polarity.
Claim 5
Dependent Claim
210 words
An interface driver circuit for transmitting signals via a transmission medium, comprising: first input means for receiving a first logic signal of a first polarity; second means for receiving a second logic signal of said first polarity; an output; third means including first and second potential sources of differing magnitudes and of said first polarity; first semiconductor switch means coupled between said first potential source and said output; second semiconductor switch means coupled between said second potential source and said output; and means for causing said first and second semiconductor switch means to respectively couple the associated one of said first and second sources of potential to said output dependent upon the state of the logic signal received at said first means, for driving said medium with the data of said first logic signal between first and second values of a voltage of said first polarity; said second means being coupled to said third means to cause said third means to be disabled whenever said second logic signal is received at said second means; and fourth means coupled between said second means and said output for driving said medium with the data of said second logic signal between said first and second values of a voltage of the remaining polarity.
Claim 6
Dependent Claim
49 words
The circuit as set forth in claim 1, wherein said third means further includes third semiconductor switch means coupled between said second means and said first means for preventing said first and second semiconductor switch means from operating if the second logic signal is present at said second means.
Claim 7
Dependent Claim
63 words
The circuit of claim 4, wherein said fourth means comprises a source of a third potential and of said remaining polarity; and semiconductor switch means coupled between said second means and said output for coupling said potential of said remaining polarity to said output when the second logic signal is received by said second means, regardless of the condition of said first signal.
Claim 8
Dependent Claim
27 words
A circuit as set fourth in claim 1, wherein said third and fourth means are adapted to drive a transmission medium comprising a twisted pair of wires.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-01 | 1983-10-01 | 1984-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-01 | 1987-10-01 | 1988-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-01 | 1991-10-01 | 1992-04-01 | $7700.00 | Window Closed / Lapsed |