Patent US4193080A successfully refreshed from Google Patents.
US4193080A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory device
Assignee: Panasonic Holdings Corp
•
Filing: 1978-11-09
•
Granted: 1980-03-11
•
Expires: 1998-11-09
Abstract
Abstract The present invention provides a memory device of MNOS FET type wherein a high concentration part and a low concentration part contact each other in the source region and the drain region, and further, double layered insulation films under the gate electrode extending across the source region and drain region are made to contact only the lower concentration part, so that an acceptor impurity is prevented from mixing into the double layered insulation films from the source region and drain region, thus greatly improving the life (number of repeated uses) of the device.
Inventors
- 👤 Susumu Koike
- 👤 Ginjiro Kambara
- 👤 Toshio Matsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
233 words
A non-volatile memory device comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region which are formed having a predetermined space between each other in said semi-conductor substrate, each region having a second conductivity type opposite to said first conductivity type; a first gate insulating layer formed on said substrate and having a uniform and very small thickness, said first gate insulating layer extending between said source region and said drain region; a second gate insulating layer formed on and coextensive with said first gate insulating layer and being substantially thicker than said first insulating layer; a gate electrode formed on said second gate insulating layer; a source electrode formed to make ohmic contact with said source region; a drain electrode formed to make ohmic contact with said drain region; said substrate further comprising: a first region extending from said source region toward said drain region and having said second conductivity type and a lower impurity concentration than said source region; a second region extending from said drain region toward said source region and having said second conductivity type and a lower impurity concentration than said drain region, said first gate insulating layer having peripheral edges on at least one part of said first extended region and on at least one part of said second extended region, but not on said source region and said drain region.
Claim 2
Dependent Claim
233 words
A non-volatile memory device comprising: a semiconductor substrate of a first conductivity type; a source region and a drain region which are formed having a predetermined space between each other in said semi-conductor substrate, each region having a second conductivity type opposite to said first conductivity type; a first gate insulating layer formed on said substrate and having a uniform and very small thickness, said first gate insulating layer extending between said source region and said drain region; a second gate insulating layer formed on and coextensive with said first gate insulating layer and being substantially thicker than said first insulating layer; a gate electrode formed on said second gate insulating layer; a source electrode formed to make ohmic contact with said source region; a drain electrode formed to make ohmic contact with said drain region; said substrate further comprising: a first region extending from said source region toward said drain region and having said second conductivity type and a lower impurity concentration than said source region; a second region extending from said drain region toward said source region and having said second conductivity type and a lower impurity concentration than said drain region, said first gate insulating layer having peripheral edges on at least one part of said first extended region and on at least one part of said second extended region, but not on said source region and said drain region.
Claim 3
Dependent Claim
18 words
The non-volatile memory device of claim 1 wherein said first gate insulating layer comprises a SiO 2 film.
Claim 4
Dependent Claim
41 words
The non-volatile memory device of claim 1 wherein said first gate insulating layer comprises an SiO 2 film formed on said substrate and said second gate insulating layer comprises an Si 3 N 4 film formed on said SiO 2 film.
Claim 5
Dependent Claim
158 words
A non-volatile memory device comprising: a semi-conductor substrate of one conductivity type; a source region and drain region of opposite conductivity formed in said substrate, said source region being a predetermined distance from said drain region, the portion of said semiconductor substrate between said source and drain regions including a gate region, a double-layered gate insulating film formed on said gate region and comprising an SiO 2 film formed on the surface of said substrate and an insulating film of Si 3 N 4 formed on and coextensive with said SiO 2 film, said Si 3 N 4 film being thicker than said SiO 2 film, each of the source and drain regions having a higher impurity concentration portion and a lower impurity concentration portion, said double-layered gate insulation film being formed on said lower impurity concentration portions and on the area of said semi-conductor substrate between said lower impurity concentration portions of said source and drain regions.
Claim 6
Dependent Claim
158 words
A non-volatile memory device comprising: a semi-conductor substrate of one conductivity type; a source region and drain region of opposite conductivity formed in said substrate, said source region being a predetermined distance from said drain region, the portion of said semiconductor substrate between said source and drain regions including a gate region, a double-layered gate insulating film formed on said gate region and comprising an SiO 2 film formed on the surface of said substrate and an insulating film of Si 3 N 4 formed on and coextensive with said SiO 2 film, said Si 3 N 4 film being thicker than said SiO 2 film, each of the source and drain regions having a higher impurity concentration portion and a lower impurity concentration portion, said double-layered gate insulation film being formed on said lower impurity concentration portions and on the area of said semi-conductor substrate between said lower impurity concentration portions of said source and drain regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-03-11 | 1983-09-10 | 1984-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-03-11 | 1987-09-10 | 1988-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-03-11 | 1991-09-10 | 1992-03-11 | $7700.00 | Window Closed / Lapsed |