CMOS-bipolar EAROM

Claim 2

A monolithic electrically alterable read only memory comprising: an array of memory cells each including an electrically alterable device and a bipolar transistor in an emitter follower configuration; row drivers, connected to the bases of said cell transistors, each including a CMOS inverter as its input and an NPN bipolar transistor in an emitter follower configuration as its output, the emitter of the output NPN transistor being connected to the bases of said cell transistors in a given row; CMOS column drivers and transmission gates; and CMOS output means.

Claim 3

The memory of claim 1 wherein said row drivers further include an N channel MOS having its gate connected to the gate of the input inverter and its drain connected to the emitter of said output NPN transistor.

Claim 4

The memory of claim 1 wherein each of said cell transistors has a P - base region and an N + emitter region.

Claim 5

The memory of claim 3 wherein said cell transistors are NPN and an N conductivity type substrate forms a common collector for said cell transistor, and including means for biasing said substrate positive.

Claim 6

The memory of claim 1 wherein said electrically alterable device is a switchable amorphous material device.

Claim 7

The memory of claim 5 wherein said switchable amorphous device has a switching threshold of greater than ten volts and said cell transistors are NPN with an emitter to base breakdown voltage of greater than twenty volts.

Claim 8

The memory of claim 1 wherein said electrically alterable device is a fuse.

Claim 9

In an electrically alterable memory array having CMOS row and column addressing buffers and CMOS output buffers and each cell including an electrically alterable device and an isolation device, the improvement comprising: said row addressing buffers each include a bipolar transistor in an emitter follower configuration as an output stage; said electrically alterables device having a switching threshold of greater than ten volts; and said isolation devices being NPN bipolar transistors in an emitter follower configuration with an emitter to base breakdown voltage of greater than twenty volts.

Claim 10

In an electrically alterable memory array having CMOS row and column addressing buffers and CMOS output buffers and each cell including an electrically alterable device and an isolation device, the improvement comprising: said row addressing buffers each include a bipolar transistor in an emitter follower configuration as an output stage; said electrically alterables device having a switching threshold of greater than ten volts; and said isolation devices being NPN bipolar transistors in an emitter follower configuration with an emitter to base breakdown voltage of greater than twenty volts.

Claim 11

The memory of claim 8 wherein all of said NPN transistors have a common collector and including means for biasing said common collector positive.

Claim 12

The memory of claim 8 wherein said NPN transistors having their bases connected to a respective emitter of said buffer transistors and means biasing said memory in a read mode and a programming mode for driving a selected NPN and buffer bipolar transistor as a Darlington amplifier.

Claim 13

The memory of claim 8 wherein said electrically alterable device is a switchable amorphous material device.

Claim 14

The memory of claim 8 wherein said input buffer includes a CMOS inverter as an input stage, said buffer transistor is an NPN transistor and said output stage includes an N channel MOS having its gate connected to the input of said inverter and its drain connected in series with the emitter of said output transistor.

Claim 15

The memory of claim 8 wherein each NPN transistor includes an N-type collector region, a P-type base region formed in said collector region having a surface impurity concentration of approximately 10 16 atoms per cubic centimeter and an N-type emitter region formed in said base region having a surface impurity concentration of approximately 5×10 19 atoms per cubic centimeter.

Claim 16

The memory of claim 13 including a base contact region formed across a boundry of said base and collector region having a surface impurity concentration of approximately 3×10 19 atoms per cubic centimeter.

Claim 17

A monolithic electrically alterable memory comprising: an array of memory cells each including an electrically alterable device and an NPN bipolar transistor in an emitter follower configuration; row drivers, each including CMOS devices and an NPN bipolar transistor output element in an emitter follower configuration, said row driver NPN transistor and respective array NPN transistors being connected in a Darlington configuration; CMOS column drivers and transmission gates; and CMOS output means.

Claim 18

A monolithic electrically alterable memory comprising: an array of memory cells each including an electrically alterable device and an NPN bipolar transistor in an emitter follower configuration; row drivers, each including CMOS devices and an NPN bipolar transistor output element in an emitter follower configuration, said row driver NPN transistor and respective array NPN transistors being connected in a Darlington configuration; CMOS column drivers and transmission gates; and CMOS output means.

Claim 19

The memory of claim 15 wherein said switchable amorphous device has a switching threshold greater than ten volts and cell NPN transistors have an emitter to base breakdown voltage of greater than 20 volts.

Claim 20

An integrated digital buffer comprising: a CMOS inverter input circuit including a first P channel MOS and a first N channel MOS having their gates connected together as the buffer input and their sources and drains connected in series between a first and second power supply terminals, an output circuit including a NPN transistor having its base connected to the interconnection of the drains of said first MOS devices, its collector connected to said first power supply terminal and its emiiter as the buffer output, and a second N channel MOS having its gate connected to the buffer input, its drain connected to the emitter of said NPN transistor and its source connected to said second power supply terminal.

Claim 21

An integrated digital buffer comprising: a CMOS inverter input circuit including a first P channel MOS and a first N channel MOS having their gates connected together as the buffer input and their sources and drains connected in series between a first and second power supply terminals, an output circuit including a NPN transistor having its base connected to the interconnection of the drains of said first MOS devices, its collector connected to said first power supply terminal and its emiiter as the buffer output, and a second N channel MOS having its gate connected to the buffer input, its drain connected to the emitter of said NPN transistor and its source connected to said second power supply terminal.