Block digital processing system for nonuniformly encoded digital words

Claim 1

A block digital processing system for nonuniformly encoded digital words including a transmitter digital processor for encoding samples of a speech signal in blocks of a predetermined number of samples, and a receiver digital processor for decoding said encoded digital words into said speech signal, wherein said transmitter digital processor comprises: a plurality of input terminals adapted to receive nonuniformly encoded digital words which have been obtained by preliminarily encoding the respective samples of said speech signal and each of which consists of a sign bit to indicate the polarity of said sample, a plurality of segment bits to indicate a range to which the amplitude value of said sample belongs and a plurality of mantissa bits to indicate at what location in said segment said amplitude value exists; shift register means connected to said input terminals for delaying said digital words by a period of n times the sampling period of said speech signal to temporarily store said samples equal in number to said n (n being an ineger); a maximum value detector connected to said shift register means for detecting a first digital word indicating the maximum amplitude value among said n digital words representing said samples and stored in said shift register means; means connected to said maximum value detector for generating a correction value so that a second digital word consisting of said segment bits and at least the most significant bit of said mantissa bits from said shift register means can be converted into a third digital word which includes said segment bits in said first digital word representative of the maximum amplitude value and which includes a maximum value that can be represented by said at least the most significant bit in said first digital word and that is concatenated subsequently to the least significant bit of said segment bits; normalizing means receiving said correction value and connected to said shift register means for converting the second digital word given from said shift register means into a normalized digital word with said correction value; reencoder means responsive to said third digital word from said normalizing means for uniformly quantizing said third digital word; and a multiplexer for transmitting the output code of said reencoder means and said block code in a multiplex fashion.