US3789392A
Expired / Lapsed
US
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Binary-code compressor
Assignee: Italtel SpA
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Filing: 1971-09-02
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Granted: 1974-01-29
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Expires: 1991-09-02
Abstract
Abstract A 12-bit word, including a polarity of sign bit Qs and up to seven initial zeroes preceding a group of significant bits, is converted into a compressed eight-bit word which retains the sign bit Qs in first position and four significant bits X, Y, Z, W in the last positions; the intervening three bits are the binary equivalent of the number of initial zeroes. These intervening bits are generated by a three-stage reverse counter which is loaded by a starting pulse after arrival of the sign bit and is stepped by successive clock pulses, stopping after seven cycles at the count 0 unless cut off earlier by the arrival of the first ''''one'''' following the sign bit in the original word. This first ''''one'''', or a timing pulse occurring seven cycles after the starting pulse, initiates the stepping of a shift register in which the bits X, Y, Z, W are entered for subsequent transfer to a synthesizing register also receiving the sign bit Qs and the reading of the reverse counter.
Inventors
- 👤 G Candiani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:03
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/50
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
123 words
A method of converting a significant part of an original binary code word with a constant number of bits including a group of significant bits preceded by up to (2m - 1) initial zeroes and followed by up to (2m - 2) insignificant bits, m being a constant greater than 1, into a compressed code word having a lesser number of bits than the original code word, comprising the steps of: a. counting the number of said initial zeroes in the original code word; b. translating said number n into an m-bit code combination; and c. constituting the compressed code word from a number of bits including said m-bit code combination and said group of significant bits with omission of said insignificant bits.
Claim 2
Independent Claim
123 words
A method of converting a significant part of an original binary code word with a constant number of bits including a group of significant bits preceded by up to (2m - 1) initial zeroes and followed by up to (2m - 2) insignificant bits, m being a constant greater than 1, into a compressed code word having a lesser number of bits than the original code word, comprising the steps of: a. counting the number of said initial zeroes in the original code word; b. translating said number n into an m-bit code combination; and c. constituting the compressed code word from a number of bits including said m-bit code combination and said group of significant bits with omission of said insignificant bits.
Claim 3
Dependent Claim
31 words
A method as defined in claim 1 wherein the original code word includes a sign bit ahead of said initial zeroes, said sign bit being transferred to the compressed code word.
Claim 4
Dependent Claim
28 words
A method as defined in claim 2 wherein said m-bit combination is inserted in the compressed code word between said sign bit and said group of significant bits.
Claim 5
Dependent Claim
32 words
A method as defined in claim 1 wherein said number n is subtracted in step b from the value (2m - 1), with conversion of the difference into said m-bit code combination.
Claim 6
Independent Claim
179 words
A system for converting a significant part of an original binary code word into a compressed code word having a lesser number of bits, comprising: timing means generating a succession of clock pulses; coding means having an output successively emitting the bits of said original code word in the rhythm of said clock pulses; counting means with m binary stages connected to said output for registering a count representing a number of up to (2m - 1) initial zeroes in said original word; detecting means connected to said output and to said counting means for stopping the latter in response to a first finite bit arriving before attainment of the full count; storage means connected to said output and jointly controlled by said timing means and said detecting means for registering a predetermined number of significant bits in said original code word occurring immediately upon the stopping of said counting means; and synthesizing means connected to said storage means and to said counting means for receiving therefrom, respectively, said significant bits and an m-bit code combination representing said count.
Claim 7
Independent Claim
179 words
A system for converting a significant part of an original binary code word into a compressed code word having a lesser number of bits, comprising: timing means generating a succession of clock pulses; coding means having an output successively emitting the bits of said original code word in the rhythm of said clock pulses; counting means with m binary stages connected to said output for registering a count representing a number of up to (2m - 1) initial zeroes in said original word; detecting means connected to said output and to said counting means for stopping the latter in response to a first finite bit arriving before attainment of the full count; storage means connected to said output and jointly controlled by said timing means and said detecting means for registering a predetermined number of significant bits in said original code word occurring immediately upon the stopping of said counting means; and synthesizing means connected to said storage means and to said counting means for receiving therefrom, respectively, said significant bits and an m-bit code combination representing said count.
Claim 8
Dependent Claim
27 words
A system as defined in claim 5 wherein said counting means comprises a reverse counter connected to be cleared by a starting pulse from said timing means.
Claim 9
Dependent Claim
46 words
A system as defined in claim 6 wherein said detecting means comprises a flip-flop with a setting input connected to said timing means for energization by said starting pulse and with a resetting input connected to said coding means for energization by said first finite bit.
Claim 10
Dependent Claim
44 words
A system as defined in claim 7 wherein said reverse counter is provided with an input circuit including a coincidence gate, connected to said flip-flop, and with a feedback path terminating at said coincidence gate for blocking same upon attainment of said full count.
Claim 11
Dependent Claim
23 words
A system as defined in claim 8 wherein said feedback path comprises an OR gate with input connections to said m binary stages.
Claim 12
Dependent Claim
31 words
A system as defined in claim 5, further comprising a direct connection from said output to said synthesizing means for transferring to the latter a sign bit preceding said initial zeroes.
Claim 13
Dependent Claim
24 words
A system as defined in claim 5 wherein said storage means comprises a shift register connected to be normally stepped by said clock pulses.
Claim 14
Dependent Claim
92 words
A system as defined in claim 11 wherein said shift register has a number of stages exceeding by one the number of significant bits to be transferred to said synthesizing means, said detecting means comprising a pulse generator alternatively responsive to said first finite bit and to a marking pulse from said timing means for introducing a finite bit into the first stage of said shift register, the latter being provided with a feedback connection for halting the stepping thereof upon arrival of said finite bit in the last of its stages.
Claim 15
Dependent Claim
52 words
A system as defined in claim 12 wherein said pulse generator comprises a one-shot monoflop connected to said timing means for precharging by a starting pulse and tripping by said marking pulse, said counting means and said said shift register being connected to said timing means for clearing by said starting pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |