MOS addressing circuits for display/memory panels

Claim 2

In an operating system for a multicelled gas discharge display/memory device, the device including a pair of opposed, spaced apart electrode arrays with proximate electrode portions of at least one electrode in each array defining the cells and the operating system including a sustainer voltage source for imposing an alternating potential voltage having a period and a predetermined maximum potential across each of the cells, an address voltages source for generating write and erase address voltages to manipulate the discharge state of individual cells between an "on state" and an "off state", isolation diodes for applying the sustainer voltage to the electrodes and for isolating the electrodes from each other, switching circuits for selectively applying the address voltages to the electrodes and a source of control signals for controlling the operation of the sustainer voltage source, the address voltages source and the switching circuits, the improvement comprising: a first substrate having a first plurality of the isolation diodes formed thereon, each one of said first plurality having one terminal connected in common with all others of said first plurality to the sustainer voltage source and another terminal connected to an associated electrode in one of the electrode arrays; and a second substrate having one of the switching circuits formed thereon including a plurality of solid state switches each having one side connected in common to the sustainer voltage source and the other side connected to an associated electrode in said one electrode array and being responsive to the control signals for selectively applying the address voltages to the associated electrode, said second substrate also having a second plurality of the isolation diodes formed thereon, each one of said second plurality being connected across an associated one of said solid state switches and poled oppositely from said first plurality of the isolation diodes.

Claim 3

An operating system according to claim 1 wherein said solid state switches are metal oxide semiconductor field effect transistors.

Claim 4

An operating system according to claim 1 wherein said second substrate has formed thereon means responsive to the control signals for generating a select signal for each electrode to be addressed in said one electrode array and wherein said solid state switches are responsive to the associated select signal for connecting the address voltages source to the associated electrode.

Claim 5

An operating system according to claim 3 wherein said select signal generating means generates said select signals in serial form and wherein said second substrate has formed thereon means for storing said select signals, said storage means being responsive to said control signals for generating said stored select signals to said plurality of solid state switches after all of said select signals for said one electrode array have been stored.

Claim 6

In an operating system for a multicelled gas discharge display/memory device, the device including a pair of opposed, spaced apart electrode arrays with proximate electrode portions of at least one electrode in each array defining the cells and the operating system including a sustainer voltage source for imposing an alternating potential voltage having a period and a predetermined maximum potential across each of the cells, an address voltages source for generating write and erase address pulses to manipulate the discharge state of individual cells between an "on state" and an "off state", isolation diodes for applying the sustainer voltage to the electrodes and for isolating the electrodes from each other, and switching circuits for selectively applying the address pulses to the electrodes, the improvement comprising: at least one integrated circuit chip having a plurality of said isolation diodes formed thereon in common cathode configuration, said common cathodes being connected to the sustainer voltage source and an anode of each of said isolation diodes connected to an associated electrode in one of the electrode arrays; at least a second integrated circuit chip having a plurality of solid state switches formed thereon, said switches having one side connected in common to the sustainer source and to the address voltages source and the other side connected individually to an associated electrode in said one electrode array, said second integrated circuit chip also having a plurality of said isolation diodes formed thereon, each of said isolation diodes being connected across an associated one of said solid state switches and poled oppositely from the isolation diodes in said one integrated circuit chip; at least a third integrated circuit chip having a plurality of the isolation diodes formed thereon in common anode configuration, said common anodes being connected to the sustainer voltage source and a cathode of each of the isolation diodes connected to an associated electrode of the other one of the electrode arrays; and at least a fourth integrated circuit chip having a plurality of solid state switches formed thereon, said switches having one side connected in common to the sustainer source and to the address voltages source and the other side connected individually to an associated electrode in said other electrode array, said fourth integrated circuit chip also having a plurality of the isolation diodes formed thereon, each of the isolation diodes being connected across an associated one of said solid state switches and poled oppositely from the isolation diodes in said third integrated circuit chip.

Claim 7

In an operating system for a multicelled gas discharge display/memory device, the device including a pair of opposed, spaced apart electrode arrays with proximate electrode portions of at least one electrode in each array defining the cells and the operating system including a sustainer voltage source for imposing an alternating potential voltage having a period and a predetermined maximum potential across each of the cells, an address voltages source for generating write and erase address pulses to manipulate the discharge state of individual cells between an "on state" and an "off state", isolation diodes for applying the sustainer voltage to the electrodes and for isolating the electrodes from each other, and switching circuits for selectively applying the address pulses to the electrodes, the improvement comprising: at least one integrated circuit chip having a plurality of said isolation diodes formed thereon in common cathode configuration, said common cathodes being connected to the sustainer voltage source and an anode of each of said isolation diodes connected to an associated electrode in one of the electrode arrays; at least a second integrated circuit chip having a plurality of solid state switches formed thereon, said switches having one side connected in common to the sustainer source and to the address voltages source and the other side connected individually to an associated electrode in said one electrode array, said second integrated circuit chip also having a plurality of said isolation diodes formed thereon, each of said isolation diodes being connected across an associated one of said solid state switches and poled oppositely from the isolation diodes in said one integrated circuit chip; at least a third integrated circuit chip having a plurality of the isolation diodes formed thereon in common anode configuration, said common anodes being connected to the sustainer voltage source and a cathode of each of the isolation diodes connected to an associated electrode of the other one of the electrode arrays; and at least a fourth integrated circuit chip having a plurality of solid state switches formed thereon, said switches having one side connected in common to the sustainer source and to the address voltages source and the other side connected individually to an associated electrode in said other electrode array, said fourth integrated circuit chip also having a plurality of the isolation diodes formed thereon, each of the isolation diodes being connected across an associated one of said solid state switches and poled oppositely from the isolation diodes in said third integrated circuit chip.

Claim 8

An operating system according to claim 5 wherein said solid state switches are metal oxide semiconductor field effect transistors.

Claim 9

An operating system according to claim 6 wherein said solid state switches formed on said second integrated circuit chip are N-channel devices and said solid state switches formed on said fourth integrated circuit chip are P-channel devices.

Claim 10

An operating system according to claim 5 including means for generating address signals and control signals representing selected ones of the electrodes to which the address voltage is to be applied and wherein each of said second and fourth integrated circuit chips includes means for decoding said address signals to generate a select signal for each of the electrodes connected to said chips, means responsive to one of said control signals for storing said select signals and means responsive to another one of said control signals for applying said select signals to the associated solid state switches whereby said solid state switches are responsive to said select signals for applying the address voltages to the electrodes.