MOS transistor driver circuits for plasma panels and similar matrix display devices

Claim 2

Driver circuitry for extending signals to first and second coordinate conductors associated with a predetermined cell of a matrix display device comprising first and second MOS transistors each comprised of first conductivity type semiconductor layer and second conductivity type drain and source regions disposed in said layer and defining a channel region therein, means for connecting the drain regions of said first and second transistors to said first and second conductors, respectively, and means for concurrently coupling respective signals at first and second potentials to the source region of said first transistor and the semiconductor layer of said second transistor, respectively, and for thereafter concurrently coupling said signals to the source region of said second transistor and the semiconductor layer of said first transistor, respectively.

Claim 3

The invention of claim 1 further comprising means for interconnecting the source of each transistor and its semiconductor layer, and biasing means for rendering the channel region of each transistor conductive when said signal at said first potential is applied to the source region thereof.

Claim 4

The invention of claim 2 further comprising means for selectively coupling first and second polarity selection signals to said first and second conductors, respectively, and means for applying said first polarity selection signals to the source region of said first transistor.

Claim 5

A driver for extending signals to a conductor defining one coordinate of a matrix display cell comprising a first MOS transistor disposed in a semiconductor layer, means for connecting the drain of said transistor to said conductor, first means for coupling sustain signals concurrently to the source of said transistor and said layer, second means operative for coupling write and erase signals to said conductor, and third means operative at least during the operation of said second means for coupling said write and erase signals to said layer.

Claim 6

A driver for extending signals to a conductor defining one coordinate of a matrix display cell comprising a first MOS transistor disposed in a semiconductor layer, means for connecting the drain of said transistor to said conductor, first means for coupling sustain signals concurrently to the source of said transistor and said layer, second means operative for coupling write and erase signals to said conductor, and third means operative at least during the operation of said second means for coupling said write and erase signals to said layer.

Claim 7

The invention of claim 4 further comprising biasing means for establishing the gate of said transistor alternately at a first potential such that its channel is rendered conductive when said sustain signals are at a predetermined level and at a second potential such that said channel is maintained nonconductive during the operation of said third means.

Claim 8

The invention of claim 5 wherein said second means includes second and third MOS transistors of a first channel conductivity type and a fourth MOS transistor of a second channel conductivity type, means for applying said write and erase signals to the cources of said second and third transistors, means for connecting the gates of said second and third transistors to the drains of said third and fourth transistors and to each other, means for connecting the source of said fourth transistor to a reference potential, and means responsive to an address signal for rendering the channel of said fourth transistor conductive.

Claim 9

A display system comprising, a display device having an array of crosspoint cells defined by respective row and column conductors, a plurality of individual row and column drivers each including an MOS sustain transistor having first conductivity type drain and source regions disposed in a second conductivity type semiconductor layer and defining a channel region therein, means for maintaining the source region of each sustain transistor at substantially the same potential as the semiconductor layer thereof, means for connecting the drain of each row driver sustain transistor to an associated one of said row conductors, means for connecting the drain of each column driver sustain transistor to an associated one of said column conductors, and means for establishing an alternating-polarity potential difference of predetermined magnitude between the source regions of said row driver sustain transistors, on the one hand, and the source regions of said column driver sustain transistors, on the other hand, each of said row drivers further including biasing means for rendering the channel region of its sustain transistor conductive in response to one polarity of said potential difference, and each of said column drivers further including biasing means for rendering the channel region of its sustain transistor conductive in response to the other polarity of said potential difference.

Claim 10

A display system comprising, a display device having an array of crosspoint cells defined by respective row and column conductors, a plurality of individual row and column drivers each including an MOS sustain transistor having first conductivity type drain and source regions disposed in a second conductivity type semiconductor layer and defining a channel region therein, means for maintaining the source region of each sustain transistor at substantially the same potential as the semiconductor layer thereof, means for connecting the drain of each row driver sustain transistor to an associated one of said row conductors, means for connecting the drain of each column driver sustain transistor to an associated one of said column conductors, and means for establishing an alternating-polarity potential difference of predetermined magnitude between the source regions of said row driver sustain transistors, on the one hand, and the source regions of said column driver sustain transistors, on the other hand, each of said row drivers further including biasing means for rendering the channel region of its sustain transistor conductive in response to one polarity of said potential difference, and each of said column drivers further including biasing means for rendering the channel region of its sustain transistor conductive in response to the other polarity of said potential difference.

Claim 11

The invention of claim 7 wherein each of said row drivers further includes circuit means operative for coupling row selection signals of a first polarity to its associated conductor, wherein each of said column drivers further includes circuit means operative for coupling column selection signals of a second polarity to its associated conductor and to the source of its sustain transistor, and wherein the biasing means of each column driver includes means for varying the gate potential of its sustain transistor to maintain the channel region of that sustain transistor nonconductive when said column selection signals are coupled to the source thereof.

Claim 12

The invention of claim 8 wherein the circuit means of each of said row and column drivers includes second, third and fourth MOS transistors, means for connecting the gates of said second and third transistors to the drains of said third and fourth transistors and to each other, means for connecting the source of said fourth transistor to a reference potential, and addressing means operative for rendering the channel region of said fourth transistor conductive, the second and third transistors of each row driver circuit means and the fourth transistor of each column driver circuit means being of a first channel conductivity type, and the second and third transistors of each column driver circuit means and the fourth transistor of each row driver circuit means being of a second channel conductivity type, said display system further comprising means for applying said row and column selection signals to the sources of the second and third transistors of said row driver circuit means and column driver circuit means, respectively.

Claim 13

The invention of claim 9 wherein said reference potential connecting mens includes a plurality of control MOS transistor each having its drain connected to the sources of a different plurality of said fourth transistors, means for connecting the sources of said control transistors to said reference potential, and means individually operative for rendering the channel regions of respective one of said control transistors conductive.