US4181942A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Program branching method and apparatus
Assignee: International Business Machines Corp
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Filing: 1978-03-31
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Granted: 1980-01-01
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Expires: 1998-03-31
Abstract
Abstract A special branch instruction used in a computing system serves as a conditional branch or as an unconditional branch as determined by the state of an internal register. This special branch instruction is used for conditional branching within or at the end of a program loop and for unconditional branching outside of such a loop.
Inventors
- 👤 Richard G. Forster
- 👤 John K. Howard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:13
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/32; G06F9/322; G06F9/325
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
284 words
A special branch instruction execution apparatus comprising: a source of information comprised of a sequence of signals having first or second binary states; a stored program processor, including addressable storage for program instructions, said instructions including a special branch instruction having operation code and branch address fields; first register means for storing information signals having first or second binary states for defining the branch mode; second register means for storing information signals having a zero binary state or information signals having a non-zero binary state for specifying the number of passes through a loop; and instruction execution means for executing the special branch instruction, said instruction execution means comprising means for generating a first signal to unconditionally branch to the address specified in said instruction branch address field responsive to sensing the presence of said special branch instruction operation code and to sensing the presence of the first binary state of information signals in said first register means; means for generating a second signal to branch to the address specified in said instruction branch address field and to decrement the stored information signals in said second register means responsive to sensing the presence of said special branch instruction operation code, responsive to sensing the second binary state of information signals in said first register means and responsive to sensing said non-zero binary state of information signals in said second register means; and means for generating a third signal to not branch responsive to sensing the presence of said special branch instruction operation code, responsive to sensing the second binary state of information signals in said first register means and responsive to sensing a zero binary state of information signals in said second register means.
Claim 2
Dependent Claim
284 words
A special branch instruction execution apparatus comprising: a source of information comprised of a sequence of signals having first or second binary states; a stored program processor, including addressable storage for program instructions, said instructions including a special branch instruction having operation code and branch address fields; first register means for storing information signals having first or second binary states for defining the branch mode; second register means for storing information signals having a zero binary state or information signals having a non-zero binary state for specifying the number of passes through a loop; and instruction execution means for executing the special branch instruction, said instruction execution means comprising means for generating a first signal to unconditionally branch to the address specified in said instruction branch address field responsive to sensing the presence of said special branch instruction operation code and to sensing the presence of the first binary state of information signals in said first register means; means for generating a second signal to branch to the address specified in said instruction branch address field and to decrement the stored information signals in said second register means responsive to sensing the presence of said special branch instruction operation code, responsive to sensing the second binary state of information signals in said first register means and responsive to sensing said non-zero binary state of information signals in said second register means; and means for generating a third signal to not branch responsive to sensing the presence of said special branch instruction operation code, responsive to sensing the second binary state of information signals in said first register means and responsive to sensing a zero binary state of information signals in said second register means.
Claim 3
Dependent Claim
20 words
The apparatus according to claim 1 wherein said branch instruction and other instructions are stored in a read-only storage apparatus.
Claim 4
Dependent Claim
29 words
The apparatus according to claim 1 additionally comprising means to set data into said first and said second register means immediately prior to the execution of said branch instruction.
Claim 5
Dependent Claim
29 words
The apparatus according to claim 1 additionally comprising means to reset said first register means prior to the execution of the next sequential instruction when no branch is taken.
Claim 6
Independent Claim
173 words
The method, in a digital computer, of branching from a first instruction sequence to a second instruction sequence comprising the steps of; decoding from said first instruction sequence a code indicating a branch instruction and a branch address; detecting the occurrence in a first register means of a first binary state of information signals; unconditionally branching to a second sequence of instructions specified by the branch address in response to the occurrence in said first register means of said first state; detecting, after the absence of the occurrence in said first register means of said first binary state, the binary state of information signals in a second register means; branching to a second sequence of instructions specified by the branch address and decrementing the information signals in said second register means in response to detecting the absence of the occurrence in said second register means of information signals having a zero binary state; and not branching in response to detecting a zero binary state in the information signals in said second register means.
Claim 7
Independent Claim
173 words
The method, in a digital computer, of branching from a first instruction sequence to a second instruction sequence comprising the steps of; decoding from said first instruction sequence a code indicating a branch instruction and a branch address; detecting the occurrence in a first register means of a first binary state of information signals; unconditionally branching to a second sequence of instructions specified by the branch address in response to the occurrence in said first register means of said first state; detecting, after the absence of the occurrence in said first register means of said first binary state, the binary state of information signals in a second register means; branching to a second sequence of instructions specified by the branch address and decrementing the information signals in said second register means in response to detecting the absence of the occurrence in said second register means of information signals having a zero binary state; and not branching in response to detecting a zero binary state in the information signals in said second register means.
Claim 8
Dependent Claim
28 words
The method of claim 5 further including the step of setting data into said first and said second register means immediately prior to execution of said branch instruction.
Claim 9
Dependent Claim
34 words
The method of claim 5 further including the step of resetting said first register means prior to the execution of the next sequential instruction in said first instruction sequence when no branch is taken.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-31 | 1983-07-02 | 1984-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-31 | 1987-07-02 | 1988-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-31 | 1991-07-02 | 1992-01-01 | $7700.00 | Window Closed / Lapsed |