Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions, in response to the occurrence of certain conditions

Claim 2

In a multi-instruction processing machine, the combination of: means for storing a sequence of instructions; decoding means responsive to a specific type of instruction in said sequence of instructions, for indicating that explicitly predetermined subsequent instructions in said sequence are to be skIpped on the occurrence of a specified condition; means for detecting the occurrence of said specified condition; and means responsive to said detection of said occurrence for skipping said explicitly predetermined instructions.

Claim 3

Apparatus in a digital computer for effecting the skipping of certain predetermined instructions in a sequence of instructions and for inhibiting the skipping of certain other predetermined instructions in said sequence of instructions, wherein each instruction includes a code portion designating the instruction type, and first and second portions which, for a specific type of instruction, designate machine parameters upon which a condition determination is to be made, and each instruction further includes a skip flag connoting that said instruction is to be skipped upon a previous successful condition determination, comprising in combination: a source of said instructions; a first plurality of storage means for receiving at least a portion of said instruction sequence from said source; a second plurality of storage means; third storage means; means for transferring said instructions from ones of said first plurality of storage means to other ones of said first plurality of storage means and to ones of said second plurality of storage means, said transferring means also capable of transfering instructions from ones of said second plurality of storage means to other ones of said second plurality of storage means; means for decoding said code portion of said instructions from a specific one of said second plurality of storage means and providing signals to said computer for processing said decoded instructions, and providing other signals upon the decoding of one of said specific type of instructions, said other signals indicative of said condition determination to be made; decoding means for decoding said first and second portions of said instruction from said specific one of said second plurality of storage means and providing a signal to said third storage means defining the machine parameters upon which said condition determination is to be made, said third storage means providing outputs representative of said condition parameters; function generation means responsive to said other signals and to said output of said third storage means for providing a first indication indicative of the detection of said specific type instruction and of a successful condition determination, and for providing a second indication indicative of the detection of one of said specified instruction and the lack of a successful condition determination; logic means responsive to said first indication and said skip flag in said specific one of said second storage means for skipping said instruction in said specific row by inhibiting the decode of said instruction; second logic means responsive to said first indication and to the skip flags of specified ones of said first and second storage means for setting a predetermined bit in the instructions of said specified ones of said first and second storage means containing instructions to be skipped; and logic responsive to said specific set bits and providing an output for shifting instructions in said sequence into said specified instructions in said sequence into said specified ones of said first and second storage means containing instructions to be skipped.

Claim 4

Apparatus in a digital computer for effecting the skipping of certain predetermined instructions in a sequence of instructions and for inhibiting the skipping of certain other predetermined instructions in said sequence of instructions, wherein each instruction includes a code portion designating the instruction type, and first and second portions which, for a specific type of instruction, designate machine parameters upon which a condition determination is to be made, and each instruction further includes a skip flag connoting that said instruction is to be skipped upon a previous successful condition determination, comprising in combination: a source of said instructions; a first plurality of storage means for receiving at least a portion of said instruction sequence from said source; a second plurality of storage means; third storage means; means for transferring said instructions from ones of said first plurality of storage means to other ones of said first plurality of storage means and to ones of said second plurality of storage means, said transferring means also capable of transfering instructions from ones of said second plurality of storage means to other ones of said second plurality of storage means; means for decoding said code portion of said instructions from a specific one of said second plurality of storage means and providing signals to said computer for processing said decoded instructions, and providing other signals upon the decoding of one of said specific type of instructions, said other signals indicative of said condition determination to be made; decoding means for decoding said first and second portions of said instruction from said specific one of said second plurality of storage means and providing a signal to said third storage means defining the machine parameters upon which said condition determination is to be made, said third storage means providing outputs representative of said condition parameters; function generation means responsive to said other signals and to said output of said third storage means for providing a first indication indicative of the detection of said specific type instruction and of a successful condition determination, and for providing a second indication indicative of the detection of one of said specified instruction and the lack of a successful condition determination; logic means responsive to said first indication and said skip flag in said specific one of said second storage means for skipping said instruction in said specific row by inhibiting the decode of said instruction; second logic means responsive to said first indication and to the skip flags of specified ones of said first and second storage means for setting a predetermined bit in the instructions of said specified ones of said first and second storage means containing instructions to be skipped; and logic responsive to said specific set bits and providing an output for shifting instructions in said sequence into said specified instructions in said sequence into said specified ones of said first and second storage means containing instructions to be skipped.

Claim 5

In a multi-instruction processing machine where instructions are issued in sequence and decoded for processing, means for skipping a subset of a predetermined set of instructions, comprising in combination: means for decoding instructions, certain of which indicate a condition upon which said subset of instructions are to be skipped; means for providing an indication of the occurrence of said condition; means responsive to said indication for marking ones of said subset of instructions to be skipped; and means responsive to said markings in subset of instructions for skipping Said subset of instructions.

Claim 6

In a multi-instruction processing machine where instructions are issued in sequence and decoded for processing, means for skipping a subset of a predetermined set of instructions, comprising in combination: means for decoding instructions, certain of which indicate a condition upon which said subset of instructions are to be skipped; means for providing an indication of the occurrence of said condition; means responsive to said indication for marking ones of said subset of instructions to be skipped; and means responsive to said markings in subset of instructions for skipping Said subset of instructions.

Claim 7

The combination of claim 3 further including means responsive to said indication for inhibiting the decoding of other ones of said certain instructions to be skipped.

Claim 8

In a data processing machine the combination of: a source of a sequence of instructions, each instruction containing a skip indicator settable to either of two stable states, said sequence of instructions containing skip instructions indicating that subsequent instructions before a succeeding skip instruction and with their skip indicators set to one of said two stable states are to be skipped in said sequence upon the detection of a predetermined machine condition; decoding means responsive to said skip instructions for indicating the predetermined machine condition to be detected; detection means for detecting said predetermined machine condition; and skipping means responsive to the detection of said predetermined machine condition for affecting the skipping of said instructions.

Claim 9

In a data processing machine the combination of: a source of a sequence of instructions, each instruction containing a skip indicator settable to either of two stable states, said sequence of instructions containing skip instructions indicating that subsequent instructions before a succeeding skip instruction and with their skip indicators set to one of said two stable states are to be skipped in said sequence upon the detection of a predetermined machine condition; decoding means responsive to said skip instructions for indicating the predetermined machine condition to be detected; detection means for detecting said predetermined machine condition; and skipping means responsive to the detection of said predetermined machine condition for affecting the skipping of said instructions.

Claim 10

In a multi-instruction processing machine, the combination of: storage means for temporarily storing a sequence of instructions from a memory, said instructions including skip instructions; first decoding means responsive to said skip instructions for generating an indication of at least one of said machine conditions to be detected; second decoding means for generating parameters of said at least one of said machine conditions; means responsive to said indication and to said generated parameters for detecting the occurrence of said at least one machine condition; and means responsive to said detecting means and coupled to said storage means for skipping explicitly predetermined instructions in said sequence by overwriting said instructions by other instructions.

Claim 11

In a multi-instruction processing machine, the combination of: storage means for temporarily storing a sequence of instructions from a memory, said instructions including skip instructions; first decoding means responsive to said skip instructions for generating an indication of at least one of said machine conditions to be detected; second decoding means for generating parameters of said at least one of said machine conditions; means responsive to said indication and to said generated parameters for detecting the occurrence of said at least one machine condition; and means responsive to said detecting means and coupled to said storage means for skipping explicitly predetermined instructions in said sequence by overwriting said instructions by other instructions.

Claim 12

In a multi-instruction processing machine wherein instructions are issued in sequence and decoded for processing, the combination of: shift-down buffer means for receiving at least a part of a sequence of instructions; first decoding means responsive to specific ones of said sequence of instructions, for indicating that explicitly predetermined instructions in said sequence are to be skipped upon the occurrence of a machine condition; second decoding means for determining parameters of said condition; storage means responsive to said second decoding means for providing an indication of the occurrence of said parameters; function generating means responsive to said first decoding means and to the indication of the occurrence of said parameters for providing an indication of the occurence of said condition; and means responsive to said indication of said condition for effecting the skipping of said explicitly predetermined instructions.

Claim 13

In a multi-instruction processing machine wherein instructions are issued in sequence and decoded for processing, the combination of: shift-down buffer means for receiving at least a part of a sequence of instructions; first decoding means responsive to specific ones of said sequence of instructions, for indicating that explicitly predetermined instructions in said sequence are to be skipped upon the occurrence of a machine condition; second decoding means for determining parameters of said condition; storage means responsive to said second decoding means for providing an indication of the occurrence of said parameters; function generating means responsive to said first decoding means and to the indication of the occurrence of said parameters for providing an indication of the occurence of said condition; and means responsive to said indication of said condition for effecting the skipping of said explicitly predetermined instructions.

Claim 14

The combination of claim 7 wherein said last-named means includes means for marking ones of said explicitly predetermined instructions in said buffer means, and means responsive to said markings for shifting unmarked ones of said instructions into portions of said buffer means containing said marked instructions, thereby electronically writing over said marked instructions.

Claim 15

The combination of claim 8 wherein said last-named means further includes means responsive to said indication for inhibiting the decoding of other ones of said predetermined instructions.