Program branching and register addressing procedures and apparatus

Claim 3

The invention as set forth in claim 1 in which the contents of an instruction address register constitute the address of the current instruction, and wherein the generating step includes the steps of producing a stream of 1 + Y pulses, and incrementing the contents of the instruction address register with the 1 + Y pulses.

Claim 4

The invention as set forth in claim 2 and further including an initial step of providing a mask and branch instruction which identifies the pair of operands to be compared and which constitutes the current instructions.

Claim 5

The invention as set forth in claim 3 wherein the comparing step is performed bit serial.

Claim 6

The invention as set forth in claim 4 wherein the comparing step is an ANDING step such that the like ordered bits of the two operands are ANDED.

Claim 7

Program branch apparatus for a computer having an instruction address register, the contents of which constitute the address of the program instruction which is currently being executed and which is stored in the computer memory, said apparatus comprising: means for comparing a pair of N bit operands for identity of bit values of a first binary significance; and means for changing the value of the contents of the instruction address register by one and by Y, where Y is N minus the order of the lowest ordered bit position in which the identity occurs and where the bit orders range from 0 to N-1.

Claim 8

Program branch apparatus for a computer having an instruction address register, the contents of which constitute the address of the program instruction which is currently being executed and which is stored in the computer memory, said apparatus comprising: means for comparing a pair of N bit operands for identity of bit values of a first binary significance; and means for changing the value of the contents of the instruction address register by one and by Y, where Y is N minus the order of the lowest ordered bit position in which the identity occurs and where the bit orders range from 0 to N-1.

Claim 9

The invention as set forth in claim 6 wherein said means for increasing include means for producing a stream of 1 + Y pulses, and means for incrementing the contents of the instruction address register with the 1 + Y pulses.

Claim 10

The invention as set forth in claim 7 and further including means for providing a mask and branch instruction which identifies the pair of operands to be compared by the comparing means and which constitutes the current instruction.

Claim 11

The invention as set forth in claim 8 wherein the comparing means includes a coincidence gate having two inputs which serially receive the like ordered bits of the two operands during N consecutive time slots such that a true value at the output of the coincidence gate corresponds to said identity of bit values of a first binary significance; and wherein said producing means includes means responsive to the first true value output of said coincidence gate to produce an enabling signal, means for producing a clock pulse during each of said consecutive time slots, and during one additional time slot, first gate means responsive to said enabling signal for passing Y of the clock pulses generated during consecutive time slots, and a further gate for combining said Y pulses and the clock pulse generated during said additional time slot so as to produce the 1 + Y stream of pulses.