Computer addressing apparatus

Claim 1

Computer apparatus for processing a list of operands, comprising: a memory for storing program instructions and a list of operands at addressable locations therein, said instructions including an execute and repeat instruction having an operation field, a terminating status field, and an address field indicative of an object instruction which has an operation field and an address field indicative of the last address in said operand list; memory addressing means for addressing said memory locations, said memory addressing means including a program register, the contents of which indicate the current instruction address, said contents being normally changed in value by ''''one'''' as each instruction is executed; an instruction register for storing each program instruction addressed by said memory addressing means; means for executing each instruction stored in said instruction register; first register means for storing said terminating status field; first means, responsive to an execute and repeat instruction being stored in the instruction register, for loading the terminating status field into said first register means; second means, responsive to said execute and repeat instruction stored in the instruction register, for providing 1. a first control signal which inhibits the normal value changing of the contents of the program register, and 2. a second control signal which enables an address modifier network; said memory address means further including third means, responsive to the address field of said execute and repeat instruction stored in the instruction register, for addressing said object instruction in order to load said object instruction into said instruction register; means, including said address modifier network, for causing said execution means to repetitively execute said object instruction, when stored in the instruction register, upon each of the operands in said operand list, one by one; second register means for storing an execution status field indicative of operating conditions at the conclusion of each execution of said object instruction; fourth means, responsive to each execution of said object instruction, for loading said execution status field into said second register means; comparison means, responsive to each execution of said object instruction, for comparing the contents of said first and second register means; and termination means, responsive to said comparison means indicating the agreement of said terminating and execution status fields, for terminating the repetitive execution of said object instruction by disabling said first and second control signals.