Patent US4175240A successfully refreshed from Google Patents.
US4175240A
Expired / Lapsed
US
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Integrated logic circuit with a current source made as a field-effect transistor
Assignee: Individual
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Filing: 1978-01-03
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Granted: 1979-11-20
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Expires: 1998-01-03
Abstract
Abstract The integrated logic circuit of the invention comprises a switching field-effect transistor and a current source, which is another field-effect transistor having its conductivity complementary to that of the switching field-effect transistor. The second field-effect transistor has its gate coupled to the source of the switching field-effect transistor, and to an electrode of a power supply its source coupled to the other power supply circuit electrode and its drain coupled to the gate of the switching field-effect transistor. The gate and the drain of the switching field-effect transistor are respectively connected to the input and the output of the circuit.
Inventors
- 👤 Vyacheslav Y. Kremlev
- 👤 Artashes R. Nazarian
- 👤 Alexei V. Lubashevsky
- 👤 Vilyam N. Kokin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09403; H03K19/09414; H10; H10D; H10D84/00; H10D84/80; H10D84/87; H10D89/00; H10D89/211; H10D89/213; H10D89/217
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
124 words
An integrated logic circuit comprising: a first field-effect transistor operating in a switching mode and having a gate, a drain and a source; a second field-effect transistor having its conductivity complementary to that of said first field-effect transistor, operating as a current source and having a gate, a drain and a source; an input electrode coupled to the gate of said first transistor and to the drain of said second transistor; an output electrode coupled to the drain of said first transistor; a first power supply circuit electrode coupled to the source of said second field-effect transistor; and a second power supply circuit electrode, which is grounded and coupled to the gate of said second transistor and to the source of said first transistor.
Claim 2
Dependent Claim
124 words
An integrated logic circuit comprising: a first field-effect transistor operating in a switching mode and having a gate, a drain and a source; a second field-effect transistor having its conductivity complementary to that of said first field-effect transistor, operating as a current source and having a gate, a drain and a source; an input electrode coupled to the gate of said first transistor and to the drain of said second transistor; an output electrode coupled to the drain of said first transistor; a first power supply circuit electrode coupled to the source of said second field-effect transistor; and a second power supply circuit electrode, which is grounded and coupled to the gate of said second transistor and to the source of said first transistor.
Claim 3
Dependent Claim
76 words
An integrated logic circuit as claimed in claim 1, further comprising: at least one additional gate of said first field-effect transistor; additional input electrodes whose number is equal to the number of said additional gates, each additional input electrode being coupled to a respective additional gate; and additional drains of said second field-effect transistor, whose number is equal to the number of said additional gates, coupled to a respective additional gate of said first field-effect transistor.
Claim 4
Dependent Claim
64 words
An integrated logic circuit as claimed in claim 2, further comprising: at least one additional field-effect transistor having its conductivity complementary to that of said first field-effect transistor and having a source coupled to the drain of said second field-effect transistor, a drain coupled to the gate of said first field-effect transistor, and a gate coupled to the source of said first field-effect transistor.
Claim 5
Dependent Claim
116 words
An integrated logic circuit as claimed in claim 2, wherein: said source of said first transistor and said gate of said second transistor are combined with an n-substrate of the circuit, said source of said second transistor is a diffusion region of p-type conductivity of said substrate, two p-regions adjacent to said diffusion region are channels of said transistor, said gates of said first transistor and said drains of said second transistor being made as additional p-regions, a first n-region in the substrate used as said drain of said first transistor and overlapping said p-regions, and a second n-region used as an ohmic contact of said substrate and connected to said second power supply circuit electrode.
Claim 6
Dependent Claim
64 words
An integrated logic circuit as claimed in claim 1, further comprising: at least one additional field-effect transistor having its conductivity complementary to that of said first field-effect transistor and having a source coupled to the drain of said second field-effect transistor, a drain coupled to the gate of said first field-effect transistor, and a gate coupled to the source of said first field-effect transistor.
Claim 7
Dependent Claim
194 words
An integrated inverter comprising: a first field-effect transistor operating in a switching mode and having a gate, a drain and a source; a second field-effect transistor having its conductivity complementary to that of said first field-effect transistor, operating as a current source and having a gate, a drain and a source; an input electrode coupled to the gate of said first transistor and to the drain of said second transistor; an output electrode coupled to the drain of said first transistor; a first power supply circuit electrode coupled to the source of said second transistor; and a second power supply circuit electrode, which is grounded and coupled to the gate of said second transistor and to the source of said first transistor; wherein said first transistor is made in the form of a planar field-effect structure with a pn junction, a vertical n(p)-channel and a source combined with an n(p)-substrate of the inverter; and wherein said current source is made in the form of a field-effect structure with a pn junction, a horizontal p(n)-channel, a drain region combined with the gate region of said first transistor and a source region combined with said substrate.
Claim 8
Dependent Claim
194 words
An integrated inverter comprising: a first field-effect transistor operating in a switching mode and having a gate, a drain and a source; a second field-effect transistor having its conductivity complementary to that of said first field-effect transistor, operating as a current source and having a gate, a drain and a source; an input electrode coupled to the gate of said first transistor and to the drain of said second transistor; an output electrode coupled to the drain of said first transistor; a first power supply circuit electrode coupled to the source of said second transistor; and a second power supply circuit electrode, which is grounded and coupled to the gate of said second transistor and to the source of said first transistor; wherein said first transistor is made in the form of a planar field-effect structure with a pn junction, a vertical n(p)-channel and a source combined with an n(p)-substrate of the inverter; and wherein said current source is made in the form of a field-effect structure with a pn junction, a horizontal p(n)-channel, a drain region combined with the gate region of said first transistor and a source region combined with said substrate.
Claim 9
Dependent Claim
184 words
An integrated inverter comprising: a first field-effect transistor operating in a switching mode and having a gate, a drain and a source; a second field-effect transistor having its conductivity complementary to that of said first transistor, operating as a current source and having a gate, a drain and a source; an input electrode coupled to the gate of said first transistor and to the drain of said second transistor; an output electrode coupled to the drain of said first transistor; a first power supply circuit electrode coupled to the source of said second transistor; and a second power supply circuit electrode, which is grounded and coupled to the gate of said second transistor and to the source of said first transistor; wherein said first transistor is made as a field-effect planar structure with a pn junction and a vertical n(p)-channel formed on a p(n)-substrate; and wherein said current source is made as a field-effect structure with a pn junction, a vertical p(n)-channel and a drain region combined with the gate region of said first transistor, and with a source region combined with said substrate.
Claim 10
Dependent Claim
184 words
An integrated inverter comprising: a first field-effect transistor operating in a switching mode and having a gate, a drain and a source; a second field-effect transistor having its conductivity complementary to that of said first transistor, operating as a current source and having a gate, a drain and a source; an input electrode coupled to the gate of said first transistor and to the drain of said second transistor; an output electrode coupled to the drain of said first transistor; a first power supply circuit electrode coupled to the source of said second transistor; and a second power supply circuit electrode, which is grounded and coupled to the gate of said second transistor and to the source of said first transistor; wherein said first transistor is made as a field-effect planar structure with a pn junction and a vertical n(p)-channel formed on a p(n)-substrate; and wherein said current source is made as a field-effect structure with a pn junction, a vertical p(n)-channel and a drain region combined with the gate region of said first transistor, and with a source region combined with said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-11-19 | 1983-05-21 | 1983-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-11-19 | 1987-05-21 | 1987-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-11-19 | 1991-05-21 | 1991-11-20 | $7700.00 | Window Closed / Lapsed |