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US4170740A
Expired / Lapsed
US
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High voltage switch and capacitive drive
Assignee: ITT Inc
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Filing: 1978-02-24
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Granted: 1979-10-09
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Expires: 1998-02-24
Abstract
Abstract A high voltage capacitive drive circuit for coupling a dc or pulsed dc input voltage from a control input to a relay having a high voltage output circuit is described in which the output of the high voltage relay circuit is electrically isolated from the control input thereto without the use of optical couplers. The combined capacitive drive circuit and high voltage switch circuit of the present invention may be integrated on a single silicon chip using conventional isolation fabrication techniques to provide good isolation between the control input and the output of the high voltage relay circuit. A pair of matched capacitive couplers are driven in a push-pull mode to pump electrical charge to a floating control circuit which turns on the high voltage relay contact. An exclusive OR circuit prevents high voltage signals on the contact terminals from inadvertently turning the contact ON or OFF by being responsive only to out of phase inputs. The described high voltage switch and capacitively coupled drive circuit is suitable for fabrication on a single semiconductor chip.
Inventors
- 👤 Joseph Pernyeszi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:03
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/567; H03K17/687; H03K17/689; H04; H04M; H04M3/00; H04M3/005
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
161 words
A solid state switch comprising: input logic means for selectively coupling an input voltage to an output of said input logic means at a predetermined frequency; means for capacitively coupling said predetermined frequency voltage from said input logic means to a pair of logic inputs, such that said predetermined frequency voltage on one of said logic inputs is out of phase with the other of said predetermined frequency voltage on the other of said logic inputs; gate means coupled to said logic inputs and responsive to the voltages on said logic inputs and having an output when the voltages on said logic inputs are out of phase; and switching means coupled to and responsive to the output of said gate means for providing either a high voltage output or a low resistance conductive path at the output thereof, in accordance with the output of said gate means, such that said high voltage output is electrically isolated from said input logic means.
Claim 2
Dependent Claim
161 words
A solid state switch comprising: input logic means for selectively coupling an input voltage to an output of said input logic means at a predetermined frequency; means for capacitively coupling said predetermined frequency voltage from said input logic means to a pair of logic inputs, such that said predetermined frequency voltage on one of said logic inputs is out of phase with the other of said predetermined frequency voltage on the other of said logic inputs; gate means coupled to said logic inputs and responsive to the voltages on said logic inputs and having an output when the voltages on said logic inputs are out of phase; and switching means coupled to and responsive to the output of said gate means for providing either a high voltage output or a low resistance conductive path at the output thereof, in accordance with the output of said gate means, such that said high voltage output is electrically isolated from said input logic means.
Claim 3
Dependent Claim
35 words
A solid state switch in accordance with claim 1 wherein said input logic means comprises a gating circuit for coupling a DC voltage from the input thereof to the output thereof at said predetermined frequency.
Claim 4
Dependent Claim
94 words
A solid state switch in accordance with claim 2 wherein said means for capacitively coupling said voltage comprises: a first capacitance coupled to the output of said input logic means and to one of said logic inputs to said gate means; an inverter coupled to the output of said input logic means and to a second capacitance, the output of said second capacitance being coupled to the other side of said logic inputs of said gate means, such that the outputs of said first and second capacitances are out of phase with each other.
Claim 5
Dependent Claim
37 words
A solid state switch in accordance with claim 3 further comprising: diode bridge means coupled to the outputs of said first and second capacitances for maintaining predetermined voltage levels at the logic inputs to said gate means.
Claim 6
Dependent Claim
18 words
A solid state switch in accordance with claim 3 wherein said gate means includes an exclusive OR gate.
Claim 7
Dependent Claim
43 words
A solid state switch in accordance with claim 3 wherein said switching means comprises a pair of switching transistors switched ON by the presence of the output of said gate means and OFF by the absence of the output of said gate means.
Claim 8
Dependent Claim
54 words
A solid state switch in accordance with claim 6 wherein said switching transistors are MOS transistors having the gates thereof coupled to the output of said gate means and for providing either a high or low resistance path between the drains thereof in response to the presence of an output from said gate means.
Claim 9
Dependent Claim
16 words
A solid state switch in accordance with claim 7 wherein said switching transistors are VMOS transistors.
Claim 10
Dependent Claim
37 words
A solid state switch in accordance with claim 3 wherein said input logic means, said means for capacitively coupling said predetermined frequency voltage, said gate means and said switching means are comprised on a single silicon chip.
Claim 11
Dependent Claim
207 words
In a telephone subscriber circuit, a signal generator for generating an electrically isolated output voltage, including signal isolation means having a plurality of solid state switches, each of said switches being coupled to a source of control signals at a control input thereof, wherein each of said solid state switches comprises: input logic means having a control input for coupling a voltage to an output of said input logic means at a predetermined frequency; means for capacitively coupling said predetermined frequency voltage from said input logic means to a pair of logic inputs, such that said predetermined frequency voltage on one of said logic inputs is of different phase than the phase of the voltage on the other of said logic inputs; gate means coupled to said logic inputs and responsive to the voltages on said logic inputs and having an output when the voltages on said logic inputs are out of phase; and switching means coupled to and responsive to the output of said gate means for providing either a high voltage output or a low resistance conductive path at the output thereof, in accordance with the output of said gate means, such that said high voltage output is electrically isolated from said input logic means.
Claim 12
Dependent Claim
207 words
In a telephone subscriber circuit, a signal generator for generating an electrically isolated output voltage, including signal isolation means having a plurality of solid state switches, each of said switches being coupled to a source of control signals at a control input thereof, wherein each of said solid state switches comprises: input logic means having a control input for coupling a voltage to an output of said input logic means at a predetermined frequency; means for capacitively coupling said predetermined frequency voltage from said input logic means to a pair of logic inputs, such that said predetermined frequency voltage on one of said logic inputs is of different phase than the phase of the voltage on the other of said logic inputs; gate means coupled to said logic inputs and responsive to the voltages on said logic inputs and having an output when the voltages on said logic inputs are out of phase; and switching means coupled to and responsive to the output of said gate means for providing either a high voltage output or a low resistance conductive path at the output thereof, in accordance with the output of said gate means, such that said high voltage output is electrically isolated from said input logic means.
Claim 13
Dependent Claim
108 words
In a telephone subscriber circuit having a plurality of improved solid state switches in accordance with claim 10 wherein said means in each of said switches for capacitively coupling said voltage comprises: a first capacitance coupled to the output of said input logic means and to one of said logic inputs to said gate means; and an inverter coupled to the output of said input logic means and to a second capacitance, the output of said second capacitance being coupled to the other of said logic inputs to said gate means, such that the outputs of said first and second capacitances are out of phase with each other.
Claim 14
Dependent Claim
32 words
In a telephone subscriber circuit having a plurality of improved solid state switches in accordance with claim 11 wherein said gate means in each of said switches includes an exclusive OR gate.
Claim 15
Dependent Claim
65 words
In a telephone subscriber circuit having a plurality of improved solid state switches in accordance with claim 12 wherein said switching transistors in each of said switches are MOS transistors having the gates thereof coupled to the output of said gate means and for providing either a high or low resistance path between the drains thereof in response to the output from said gate means.
Claim 16
Dependent Claim
30 words
In a telephone subscriber circuit having a plurality of improved solid state switches in accordance with claim 13 wherein said switching transistors in each of said switches are VMOS transistors.
Claim 17
Dependent Claim
51 words
In a telephone subscriber circuit having a plurality of improved solid state switches in accordance with claim 11 wherein in each of said switches said input logic means, said means for capacitively coupling said predetermined frequency voltage, said gate means and said switching means are comprised on a single silicon chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-08 | 1983-04-09 | 1983-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-08 | 1987-04-09 | 1987-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-08 | 1991-04-09 | 1991-10-09 | $7700.00 | Window Closed / Lapsed |