Electronic apparatus using complementary MOS transistor dynamic clocked logic circuits

Claim 2

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable period of said timer circuit means by applying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; dynamic clocked logic circuits each having at least one input, an output having a storage capacitance, and first and second clock inputs; each of said logic circuits being alternately enabled and disabled by a complementary pair of clock pulses applied to said first and second clock inputs, and while enabled each logic circuit producing output signals at said outputs whose voltage level depends upon the voltage level at said inputs and while disabled storing said output signals in said storage capacitance; and clock pulse supplying means coupled with said timer circuit means for supplying clock pulses to said first and second clock inputs of said dynamic clocked logic circuits during said enable periods of said timer circuit means, and for supplying disabling voltages with fixed levels to said first and second clock inputs of said dynamic clocked logic circuits during said disable periods of said timer circuit

Claim 3

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by applying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; dynamic clocked logic circuits each having at least one input, an output having a storage capacitance, and first and second clock inputs, each of said logic circuits being alternately enabled and disabled by a complementary pair of clock pulses applied to said first and second clock inputs, and while enabled each logic circuit producing output signals at said outputs whose voltage level depends upon the voltage level at said inputs, and while disabled, storing said output signals in said storage capacitance; clock pulse supplying means coupled to said timer circuit means for supplying clock pulses to said first and second clock inputs of said dynamic clocked logic circuits during said enable periods of said timer circuit means, and supplying to said first and second clock inputs of said logic circuits voltages with such a fixed level as to disable said dynamic clocked logic circuits during said disable periods of said timer circuit means; and means coupled to said outputs of said clocked logic circuits and to said timer circuit means for supplying a fixed level potential to said storage capacitance during said disable periods of said timer circuit means.

Claim 4

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by applying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; dynamic clocked logic circuits each having at least one input, an output having a storage capacitance, and first and second clock inputs, each of said logic circuits being alternately enabled and disabled by a complementary pair of clock pulses applied to said first and second clock inputs, and while enabled each logic circuit producing output signals at said outputs whose voltage level depends upon the voltage level at said inputs, and while disabled, storing said output signals in said storage capacitance; clock pulse supplying means coupled to said timer circuit means for supplying clock pulses to said first and second clock inputs of said dynamic clocked logic circuits during said enable periods of said timer circuit means, and supplying to said first and second clock inputs of said logic circuits voltages with such a fixed level as to disable said dynamic clocked logic circuits during said disable periods of said timer circuit means; and means coupled to said outputs of said clocked logic circuits and to said timer circuit means for supplying a fixed level potential to said storage capacitance during said disable periods of said timer circuit means.

Claim 5

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by applying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; first and second clocked inverters each having an input, an output having a storage capacitance, and first and second clock inputs, said inverters connected in cascade fashion with the output of said first clocked complementary inverter connected to the input of said second clocked inverter, said first and second inverters each being periodically enabled and disabled by complementary clock signals applied to said first and second clock inputs and while enabled said inverters providing an output signal to said output capacitance which is the inverse of an input signal applied to said input and while disabled storing said output signal at said storage capacitance, said first and second clocked complementary inverters being enabled in different phases; and clock pulse supplying means coupled to said timer circuit means for supplying clock signals to said first and second clock inputs of said first and second clocked inverters during said enable period of said timer circuit means, and supplying voltages with fixed levels to said first and second clock inputs of said first and second clocked inverters to enable said first and second clocked inverters during said disable period of said timer circuit means.

Claim 6

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by applying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; first and second clocked inverters each having an input, an output having a storage capacitance, and first and second clock inputs, said inverters connected in cascade fashion with the output of said first clocked complementary inverter connected to the input of said second clocked inverter, said first and second inverters each being periodically enabled and disabled by complementary clock signals applied to said first and second clock inputs and while enabled said inverters providing an output signal to said output capacitance which is the inverse of an input signal applied to said input and while disabled storing said output signal at said storage capacitance, said first and second clocked complementary inverters being enabled in different phases; and clock pulse supplying means coupled to said timer circuit means for supplying clock signals to said first and second clock inputs of said first and second clocked inverters during said enable period of said timer circuit means, and supplying voltages with fixed levels to said first and second clock inputs of said first and second clocked inverters to enable said first and second clocked inverters during said disable period of said timer circuit means.

Claim 7

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by applying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; first and second clocked inverters each having an input, an output having a storage capacitance, and first and second clock inputs, said inverters being connected in cascade fashion with the output of said first clocked inverter connected to the input of said second clocked inverter, said first and second clocked inverters each being periodically enabled and disabled by complementary clock signals applied to said first and second clock inputs; while enabled said inverters providing an output signal at said output which is the inverse of an input signal applied to said input and while disabled storing said output signal at said capacitance, said first and second clocked inverters being enabled in different phase; clock pulse supplying means coupled to said timer circuit means for supplying clock signals to said first and second clock inputs of said first and second clocked inverters during said enable period of said timer circuit means, and for supplying to said first and second clock inputs of said first and second clocked inverters output voltages with fixed levels to disable said first clocked inverter and enable said second clocked inverter during said disable period of said timer circuit means; and means coupled with the output of said first clocked inverter for supplying a potential with a fixed level to said output capacitance during disable period of said timer circuit means.

Claim 8

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by applying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; first and second clocked inverters each having an input, an output having a storage capacitance, and first and second clock inputs, said inverters being connected in cascade fashion with the output of said first clocked inverter connected to the input of said second clocked inverter, said first and second clocked inverters each being periodically enabled and disabled by complementary clock signals applied to said first and second clock inputs; while enabled said inverters providing an output signal at said output which is the inverse of an input signal applied to said input and while disabled storing said output signal at said capacitance, said first and second clocked inverters being enabled in different phase; clock pulse supplying means coupled to said timer circuit means for supplying clock signals to said first and second clock inputs of said first and second clocked inverters during said enable period of said timer circuit means, and for supplying to said first and second clock inputs of said first and second clocked inverters output voltages with fixed levels to disable said first clocked inverter and enable said second clocked inverter during said disable period of said timer circuit means; and means coupled with the output of said first clocked inverter for supplying a potential with a fixed level to said output capacitance during disable period of said timer circuit means.

Claim 9

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by supplying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; first and second clocked complementary inverters each having an input, an output having a storage capacitance, and first and second clock inputs, said inverters being connected in cascade fashion with the output of said first clocked inverter connected to the input of said second clocked inverter, said first and second clocked inverters each being periodically enabled and disabled by complementary clock pulses applied to said first and second clock inputs and said inverters providing while enabled an output signal at said output which is the inverse of an input signal applied to said input and storing while disabled said output signal at said output capacitance, said first and second clocked complementary inverters being enabled in different phase; clock pulse supplying means coupled with said timer circuit means for supplying a complementary pair of clock pulses to said first and second clocks inputs to said first and second clocked inverters during said enable periods of said timer circuit means, and for supplying to said first and second clock inputs output voltages with such fixed levels as to disable said first clocked inverter and enable said second clocked inverter during said disable periods of said timer circuit means; and a third clocked inverter which is enabled during the disabled period of said timer circuit means to feed back the output of said second clocked inverter to the input thereof.

Claim 10

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by supplying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; first and second clocked complementary inverters each having an input, an output having a storage capacitance, and first and second clock inputs, said inverters being connected in cascade fashion with the output of said first clocked inverter connected to the input of said second clocked inverter, said first and second clocked inverters each being periodically enabled and disabled by complementary clock pulses applied to said first and second clock inputs and said inverters providing while enabled an output signal at said output which is the inverse of an input signal applied to said input and storing while disabled said output signal at said output capacitance, said first and second clocked complementary inverters being enabled in different phase; clock pulse supplying means coupled with said timer circuit means for supplying a complementary pair of clock pulses to said first and second clocks inputs to said first and second clocked inverters during said enable periods of said timer circuit means, and for supplying to said first and second clock inputs output voltages with such fixed levels as to disable said first clocked inverter and enable said second clocked inverter during said disable periods of said timer circuit means; and a third clocked inverter which is enabled during the disabled period of said timer circuit means to feed back the output of said second clocked inverter to the input thereof.

Claim 11

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by supplying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; a shift register with a plurality of stages, each stage reading in input data applied to an input thereof in response to a first complementary pair of pulses and reading out the input data at an output thereof in response to a second complementary pair of pulses, said first and second clock pulses being successively applied to each stage; and clock pulse signal supplying means coupled with said timer circuit means for supplying said first complementary pair of pulses and said second complementary pair of pulses to each stage of said shift register during said enable periods of said timer circuit means and supplying a first pair of fixed voltages and a second pair of fixed voltages to each stage of said shift register during said disable periods of said timer circuit means, said first pair of fixed voltages having the same levels as those of said first complementary pair of pulses when the input data is read in and said second pair of fixed voltages having the same levels as those of said second complementary pair of pulses when the input data is read out.

Claim 12

An electronic apparatus comprising: timer circuit means having enable and disable periods; timer circuit enabling means for initiating said enable periods of said timer circuit means by supplying a control signal to said timer circuit means to enable said timer circuit means to produce at the output thereof a fixed level voltage for a fixed time; a shift register with a plurality of stages, each stage reading in input data applied to an input thereof in response to a first complementary pair of pulses and reading out the input data at an output thereof in response to a second complementary pair of pulses, said first and second clock pulses being successively applied to each stage; and clock pulse signal supplying means coupled with said timer circuit means for supplying said first complementary pair of pulses and said second complementary pair of pulses to each stage of said shift register during said enable periods of said timer circuit means and supplying a first pair of fixed voltages and a second pair of fixed voltages to each stage of said shift register during said disable periods of said timer circuit means, said first pair of fixed voltages having the same levels as those of said first complementary pair of pulses when the input data is read in and said second pair of fixed voltages having the same levels as those of said second complementary pair of pulses when the input data is read out.

Claim 13

An electronic apparatus accordng to claim 6, further comprising means for positively feeding back the output of said shift register to the input thereof.

Claim 14

An electronic apparatus according to claim 6, further comprising inverter means for negatively feeding back the output of said shift register to the input thereof, and means providing in a closed loop including said inverter and said shift register for making constant the output levels at respective stages of said shift register means during the disable periods of said timer circuit means.

Claim 15

An electronic apparatus according to claim 6, further comprising means for supplying an input voltage with a fixed level to the input of said shift register means during the disable period of said timer circuit means.

Claim 16

An electronic apparatus comprising: timer circuit means; timer circuit enabling means with a plurality of keys to enable said timer circuit means in response to the actuation of one of said keys thereby to provide a fixed level voltage for a fixed time; dynamic clocked logic circuits each having an input, an output having a storage capacitance, and first and second clock inputs; said logic circuits each being periodically enabled and disabled by a complementary pair of clock pulses applied to said first and second clock inputs said logic circuits producing at said outputs an output signal whose voltage level depends on a voltage level of an input signal applied to said input while said logic circuits are enabled and storing said output signal at said storage capacitance while said logic circuits are disabled; and clock signal supplying means coupled with said timer circuit means for producing and supplying complementary clock pulses to said first and second clock inputs of said logic circuits when said timer circuit means is enabled, and for producing and supplying disabling fixed level voltages to said first and second clock inputs of said logic circuits when said timer circuit means is not enabled.

Claim 17

An electronic apparatus comprising: timer circuit means; timer circuit enabling means with a plurality of keys to enable said timer circuit means in response to the actuation of one of said keys thereby to provide a fixed level voltage for a fixed time; dynamic clocked logic circuits each having an input, an output having a storage capacitance, and first and second clock inputs; said logic circuits each being periodically enabled and disabled by a complementary pair of clock pulses applied to said first and second clock inputs said logic circuits producing at said outputs an output signal whose voltage level depends on a voltage level of an input signal applied to said input while said logic circuits are enabled and storing said output signal at said storage capacitance while said logic circuits are disabled; and clock signal supplying means coupled with said timer circuit means for producing and supplying complementary clock pulses to said first and second clock inputs of said logic circuits when said timer circuit means is enabled, and for producing and supplying disabling fixed level voltages to said first and second clock inputs of said logic circuits when said timer circuit means is not enabled.