Complex logical fault detection apparatus and method

Claim 3

The method of testing a logic circuit as claimed in claim 1 wherein: an error condition is indicated in step (k) only when additionally the non-identical compared transition count or final logic state is not tagged indeterminate.

Claim 4

The method of testing a logic circuit as claimed in claim 1 and additionally comprising the step of: indicating an error condition with an indeterminate state if either the compared transition count or final logic state associated with a particular binary test pattern is not identical and is tagged as indeterminate.

Claim 5

Apparatus for testing a logic circuit having a binary input thereto and a binary output therefrom for error producing malfunctions comprising: (a) means for applying a binary signal to the input; (b) means for sensing the binary output; (c) means connected to said sensing means for sensing the logic state of the output; (d) means connected to said logic state sensing means for counting transitions in the logic state of the output; (e) control means connected to said signal applying means, said output logic state sensing means and said counting means, said control means including logic for accomplishing the steps of: (1) applying a plurality of preselected binary test patterns to the input of a first known good identical logic circuit according to a preselected sequence; (2) counting the number of transitions in logic state of the output of the first known good identical logic circuit from the application of each binary test pattern until a stabilized output state is reached; (3) saving the number of transitions counted and the logic state of the stabilized output for each binary test pattern of the first known good identical logic circuit; (4) applying the plurality of preselected binary test patterns used in step (1) to the input of a second known good identical logic circuit according to the sequence used in step (1); (5) counting the number of transitions in logic state of the output of the second known good identical logic circuit from the application of each binary test pattern until a stabilized output state is reached; (6) comparing the transitions counted and final logic state of the first known good identical logic circuit to those of the second known good identical logic circuit for each test pattern; (7) tagging as an indeterminate value each transition count and logic state saved in step (3) which does not compare identically with the respective transition count and logic state determined for the second known good identical logic circuit; (8) applying the plurality of preselected binary test patterns used in step (1) to the input of the logic circuit to be tested according to the sequence used in step (1); (9) counting the number of transitions in logic state of the output of the logic circuit being tested from the application of each binary test pattern until a stabilized output state is reached; (10) comparing the transitions counted and final logic states as saved in step (3) and tagged in step (7) to those of the logic circuit being tested for each test pattern; and, (11) indicating an error condition if either the compared transition count or final logic state associated with a test pattern is not identical.

Claim 6

Apparatus for testing a logic circuit having a binary input thereto and a binary output therefrom for error producing malfunctions comprising: (a) means for applying a binary signal to the input; (b) means for sensing the binary output; (c) means connected to said sensing means for sensing the logic state of the output; (d) means connected to said logic state sensing means for counting transitions in the logic state of the output; (e) control means connected to said signal applying means, said output logic state sensing means and said counting means, said control means including logic for accomplishing the steps of: (1) applying a plurality of preselected binary test patterns to the input of a first known good identical logic circuit according to a preselected sequence; (2) counting the number of transitions in logic state of the output of the first known good identical logic circuit from the application of each binary test pattern until a stabilized output state is reached; (3) saving the number of transitions counted and the logic state of the stabilized output for each binary test pattern of the first known good identical logic circuit; (4) applying the plurality of preselected binary test patterns used in step (1) to the input of a second known good identical logic circuit according to the sequence used in step (1); (5) counting the number of transitions in logic state of the output of the second known good identical logic circuit from the application of each binary test pattern until a stabilized output state is reached; (6) comparing the transitions counted and final logic state of the first known good identical logic circuit to those of the second known good identical logic circuit for each test pattern; (7) tagging as an indeterminate value each transition count and logic state saved in step (3) which does not compare identically with the respective transition count and logic state determined for the second known good identical logic circuit; (8) applying the plurality of preselected binary test patterns used in step (1) to the input of the logic circuit to be tested according to the sequence used in step (1); (9) counting the number of transitions in logic state of the output of the logic circuit being tested from the application of each binary test pattern until a stabilized output state is reached; (10) comparing the transitions counted and final logic states as saved in step (3) and tagged in step (7) to those of the logic circuit being tested for each test pattern; and, (11) indicating an error condition if either the compared transition count or final logic state associated with a test pattern is not identical.

Claim 7

The apparatus claimed in claim 4 wherein: said logic is adapted to indicate an error condition in step (k) only when additionally the non-identical compared transition count or final logic state is not tagged indeterminate.

Claim 8

The apparatus claimed in claim 4 wherein: said logic is additionally adapted to indicate an error condition with an indeterminate state if either the compared transition count or final logic state associated with a particular binary test pattern is not identical and is tagged as indeterminate.

Claim 9

The apparatus claimed in claim 4 and additionally comprising: (a) display means for displaying locations on a logic circuit where a sensing probe is to be placed; and, (b) a sensing probe connected to said logic state sensing means and adapted to be connected to points in a logic circuit being tested between the input and output thereof.

Claim 10

The apparatus claimed in claim 7 wherein said control means includes logic for accomplishing the steps of: (a) displaying a request that an operator connect said probe to a point intermediate the input and output of a first known good identical logic circuit prior to the execution of step (1) of claim 4; (b) displaying a request that an operator connect said probe to the intermediate point used in step (a) of a second known good identical logic circuit, prior to execution, of step (4) of claim 4; and where step (11) of claim 4 wherein the indicated condition is displayed.