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Patent US4156283A successfully refreshed from Google Patents.
US4156283A
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US
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Multiplier circuit
Assignee: Tektronix Inc
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Filing: 1977-10-03
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Granted: 1979-05-22
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Expires: 1997-10-03
Abstract
Abstract A linear analog multiplier circuit for multiplying electrical quantities comprises a pair of differentially connected nonlinear control devices, for example, transistors, and at least one further semiconductor junction device exhibiting logarithmic characteristics coupled thereto for compensating for the nonlinear properties of the control devices.
Inventors
- 👤 Barrie Gilbert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:06
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; G; G06; G06G; G06G7/00; G06G7/12; G06G7/24; H03F; H03F1/00; H03F1/32; H03F1/3211
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
149 words
A multiplier circuit, comprising: a differential amplifier employing a pair of semiconductor junction devices characterized by exponential operating characteristics for receiving a first electrical value and a second electrical value representative of factors to be multiplied and for nonlinearly processing said electrical values to produce a third electrical value representative of the product of said factors; and at least one further semiconductor junction device coupled to a junction of one of said pair of semiconductor junction devices, and characterized by an exponential operating chracteristic substantially identical to the chracteristics exhibited by said pair of devices. wherein the exponential operating characteristics of said pair of devices causes a nonlinear distortion of at least one of said first and second values, and the exponential operating characteristic of said further device causes a nonlinear predistortion of said one of said values to substantially cancel the distortion to provide a linear product thereby.
Claim 2
Dependent Claim
149 words
A multiplier circuit, comprising: a differential amplifier employing a pair of semiconductor junction devices characterized by exponential operating characteristics for receiving a first electrical value and a second electrical value representative of factors to be multiplied and for nonlinearly processing said electrical values to produce a third electrical value representative of the product of said factors; and at least one further semiconductor junction device coupled to a junction of one of said pair of semiconductor junction devices, and characterized by an exponential operating chracteristic substantially identical to the chracteristics exhibited by said pair of devices. wherein the exponential operating characteristics of said pair of devices causes a nonlinear distortion of at least one of said first and second values, and the exponential operating characteristic of said further device causes a nonlinear predistortion of said one of said values to substantially cancel the distortion to provide a linear product thereby.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-21 | 1982-11-20 | 1983-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-21 | 1986-11-20 | 1987-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-21 | 1990-11-20 | 1991-05-22 | $7700.00 | Window Closed / Lapsed |