Logarithmic multiplier-divider

Claim 1

A CIRCUIT FOR MULTIPLYING A PAIR OF QUANTITIES REPRESENTED BY CURRENT INPUTS COMPRISNG A FIRST AND SECOND INPUT TRANSISTOR, EACH HAVING AN EMITTER, BASE, AND COLLECTOR AND HAVING ITS BASE AND COLLECTOR CONNECTED, SAID INPUT TRANSISTORS OPERABLE TO PRODUCE A VOLTAGE PROPORTIONAL TO THE LOGARITHM OF THE INPUT CURRENT, SAID TRANSISTORS CONNECTED TO EACH OTHER IN A SERIES ADDITIVE RELATIONSHIP AND EACH HAVING A PAIR OF INPUT TERMINALS CONNECTED BETWEEN ITS BASE AND EMITTER, AN ELECTRICAL MEANS CONNECTED IN SERIES WITH SAID FIRST AND SECOND INPUT TRANSISTORS FOR PRODUCING A VOLTAGE TO REDUCE THE SUM VOLTAGE OF SAID FIRST AND SECOND TRANSISTORS AND HAVING SUBSTANTIALLY THE SAME TEMPERATURE VOLTAGE OPERATING CHARACTERISTICS AS SAID FIRTS AND SECOND INPUT TRANSISTORS, AN OUTPUT TRANSISTOR HAVING AN EMITTER, COLLECTOR, AND BASE, SAID FIRST AND SECOND INPUT TRANSISTORS AND SAID ELECTRICAL MEANS CONNECTED ACROSS SAID BASE AND EMITTER OF SAID OUTPUT TRANSISTOR, SAID OUTPUT TRANSISTOR OPERABLE TO PRODUCE THROUGH ITS COLLECTOR A CURRENT OUTPUT PROPORTIONAL TO THE ANTILOGARITHM OF THE SUM OF THE VOLTAGE APPLIED BETWEEN ITS EMITTER AND BASE.