US3304419A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid-state analog multiplier circuit
Assignee: Individual
•
Filing: 1963-07-31
•
Granted: 1967-02-14
•
Expires: 1983-07-31
Abstract
No abstract record available.
Inventors
- 👤 Jr Wright H Huntley
- 👤 Tammaru Enn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:31
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/24
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
60 words
A SOLID-STATE ANALOG MULTIPLOER CIRCUIT COMPRISING: A PAIR OF SEMICONDUCTOR JUNCTION DIODES, OPPOSITE POLARITY TERMINALS OF SAID DIODES BEING CONNECTED TO A COMMON POTENTIAL POINT SO THAT INPUT CURRENTS THROUGH SAID DIODES DEVELOP A VOLTAGE AT THE REMAINING DIODE TERMINALS WHICH VARIES AS THE SUM OF THE LOGARITHMS OF THE CURRENTS THROUGH EACH OF SAID DIODES; AND A FLOATING-INPUT, COMPLEMENTARY
Claim 2
Dependent Claim
60 words
A SOLID-STATE ANALOG MULTIPLOER CIRCUIT COMPRISING: A PAIR OF SEMICONDUCTOR JUNCTION DIODES, OPPOSITE POLARITY TERMINALS OF SAID DIODES BEING CONNECTED TO A COMMON POTENTIAL POINT SO THAT INPUT CURRENTS THROUGH SAID DIODES DEVELOP A VOLTAGE AT THE REMAINING DIODE TERMINALS WHICH VARIES AS THE SUM OF THE LOGARITHMS OF THE CURRENTS THROUGH EACH OF SAID DIODES; AND A FLOATING-INPUT, COMPLEMENTARY
References Cited (Backward Citations)
US3206619A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1970-02-13 | 1970-08-15 | 1971-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1974-02-13 | 1974-08-15 | 1975-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1978-02-13 | 1978-08-15 | 1979-02-14 | $7700.00 | Window Closed / Lapsed |