High temperature refractory metal contact assembly and multiple layer interconnect structure

Claim 1

A method of forming a complementary MOS integrated circuit structure comprising the steps of: providing an N type silicon body having a surface, forming a P- region in the surface of the body, forming spaced N+ regions within the P- region, forming spaced P+ regions in the surface of the body, forming isolation rings in the surface of the body surrounding and isolating said transistors, forming a first insulating layer on the surface of the body, forming a refractory metal sandwich on the upper surface of the first insulating layer, formation of said sandwich including the steps of forming a first silicon layer on the upper surface of the first insulating layer, forming a relatively thin refractory metal layer on the first silicon layer, and forming a second silicon layer on the upper surface of the refractory metal layer, providing one portion of the refractory metal sandwich which overlies the body surface between the spaced P+ regions to form the P channel transistor gate, providing another portion of the refractory metal sandwich which overlies the body surface between said spaced N+ regions to form the N channel transistor gate, forming a second insulating layer on the upper surface of the refractory metal sandwich, forming an additional metal layer on the upper surface of the second insulating layer, selectively dividing the refractory metal sandwich and the additional metal layer into portions having interconnecting segments which extend through intervening layers to selectively interconnect portions of the metal layers and selectively contact the upper surface of the transistor regions to form an integrated circuit.

Claim 2

A method of forming a complementary MOS integrated circuit structure comprising the steps of: providing an N type silicon body having a surface, forming a P- region in the surface of the body, forming spaced N+ regions within the P- region, forming spaced P+ regions in the surface of the body, forming isolation rings in the surface of the body surrounding and isolating said transistors, forming a first insulating layer on the surface of the body, forming a refractory metal sandwich on the upper surface of the first insulating layer, formation of said sandwich including the steps of forming a first silicon layer on the upper surface of the first insulating layer, forming a relatively thin refractory metal layer on the first silicon layer, and forming a second silicon layer on the upper surface of the refractory metal layer, providing one portion of the refractory metal sandwich which overlies the body surface between the spaced P+ regions to form the P channel transistor gate, providing another portion of the refractory metal sandwich which overlies the body surface between said spaced N+ regions to form the N channel transistor gate, forming a second insulating layer on the upper surface of the refractory metal sandwich, forming an additional metal layer on the upper surface of the second insulating layer, selectively dividing the refractory metal sandwich and the additional metal layer into portions having interconnecting segments which extend through intervening layers to selectively interconnect portions of the metal layers and selectively contact the upper surface of the transistor regions to form an integrated circuit.