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US4151019A
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Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
Assignee: Toshiba Corp
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Filing: 1977-08-05
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Granted: 1979-04-24
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Expires: 1997-08-05
Abstract
Abstract A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.
Inventors
- 👤 Yukuya Tokumaru
- 👤 Masanori Nakai
- 👤 Satoshi Shinozaki
- 👤 Junichi Nakamura
- 👤 Shintaro Ito
- 👤 Yoshio Nishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:39
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/65
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
190 words
A method of manufacturing an integrated injection logic semiconductor device comprising the steps of forming a semiconductor layer of the opposite conductivity type on a semiconductor substrate of one conductivity type; forming an insulation film on said semiconductor layer of the opposite conductivity type; forming first and second openings through said insulation film; doping an impurity of said one conductivity type into said semiconductor layer of the opposite conductivity type through said first opening in a nonoxidizing atmosphere thereby forming a first one conductivity type region reaching said semiconductor substrate; doping an impurity into said first region of the first conductivity type and said semiconductor layer of the opposite conductivity type through said first and second openings in an oxidizing atmosphere thereby forming first and second opposite conductivity type regions completely within said first one conductivity type region and said semiconductor layer of the opposite conductivity type respectively; forming a third opening through said insulation film; and doping an impurity of said one conductivity type into said selected portion of the semiconductor layer of the opposite conductivity type through said third opening thereby forming a second one conductivity type region.
Claim 2
Independent Claim
190 words
A method of manufacturing an integrated injection logic semiconductor device comprising the steps of forming a semiconductor layer of the opposite conductivity type on a semiconductor substrate of one conductivity type; forming an insulation film on said semiconductor layer of the opposite conductivity type; forming first and second openings through said insulation film; doping an impurity of said one conductivity type into said semiconductor layer of the opposite conductivity type through said first opening in a nonoxidizing atmosphere thereby forming a first one conductivity type region reaching said semiconductor substrate; doping an impurity into said first region of the first conductivity type and said semiconductor layer of the opposite conductivity type through said first and second openings in an oxidizing atmosphere thereby forming first and second opposite conductivity type regions completely within said first one conductivity type region and said semiconductor layer of the opposite conductivity type respectively; forming a third opening through said insulation film; and doping an impurity of said one conductivity type into said selected portion of the semiconductor layer of the opposite conductivity type through said third opening thereby forming a second one conductivity type region.
Claim 3
Dependent Claim
248 words
The method according to claim 1 wherein said first one conductivity type region is formed by the steps of applying a silicon nitride film on the portions of said semiconductor layer of the opposite conductivity type which are exposed through said first and second openings and on said insulation film, forming a first silicon oxide film incorporated with an impurity of said one conductivity type on said silicon nitride film; removing with an etching solution said silicon oxide film and said silicon nitride film except the portion of said silicon nitride film and the portion of said silicon oxide film confronting said second opening for exposing again said first opening, removing the remaining portion of said silicon oxide film with an etching solution; applying a second silicon oxide film incorporated with an impurity of said one conductivity type onto the surface portion of said silicon nitride film exposed as a result of the removal of said silicon oxide film, the surface portion of said semiconductor layer of the opposite conductivity typed exposed by said reexposed first opening and onto said insulation film, diffusing said impurity of the one conductivity type contained in said second silicon oxide film into said semiconductor layer of the opposite conductivity type through said first opening by treating the assembly thus obtained in a high temperature nonoxidizing atmosphere, and removing with an etching solution portions of said second silicon oxide film and said silicon nitride film for exposing again said first and second openings.
Claim 4
Independent Claim
242 words
A method of manufacturing an integrated injection logic semiconductor device in a selected portion of a semiconductor layer comprising the steps of preparing a semiconductor substrate of one conductivity type; forming said semiconductor layer of the opposite conductivity type on said semiconductor substrate of one conductivity type; forming an insulation film on said selected portion of the semiconductor layer of the opposite conductivity type; forming first and second openings through said insulation film; selectively doping an impurity of the one conductivity type into said semiconductor layer of the opposite conductivity type through said first opening in a non-oxidizing atmosphere thereby forming a first region of said one conductivity type which reaches said semiconductor substrate; doping an impurity of the opposite conductivity type into said first region of the one conductivity type and into said semiconductor layer of opposite conductivity type respectively through said first and second openings in an oxidizing atmosphere thereby forming first and second regions of opposite conductivity type completely within said first region of the one conductivity type and said selected portion of the semiconductor layer of the opposite conductivity type respectively; forming a third opening through said insulation film; and doping an impurity of the one conductivity type into said selected portion of the semiconductor layer of the opposite conductivity type through said third opening in an oxidizing atmosphere thereby forming a second region of the one conductivity type in said semiconductor layer of the opposite conductivity type.
Claim 5
Independent Claim
242 words
A method of manufacturing an integrated injection logic semiconductor device in a selected portion of a semiconductor layer comprising the steps of preparing a semiconductor substrate of one conductivity type; forming said semiconductor layer of the opposite conductivity type on said semiconductor substrate of one conductivity type; forming an insulation film on said selected portion of the semiconductor layer of the opposite conductivity type; forming first and second openings through said insulation film; selectively doping an impurity of the one conductivity type into said semiconductor layer of the opposite conductivity type through said first opening in a non-oxidizing atmosphere thereby forming a first region of said one conductivity type which reaches said semiconductor substrate; doping an impurity of the opposite conductivity type into said first region of the one conductivity type and into said semiconductor layer of opposite conductivity type respectively through said first and second openings in an oxidizing atmosphere thereby forming first and second regions of opposite conductivity type completely within said first region of the one conductivity type and said selected portion of the semiconductor layer of the opposite conductivity type respectively; forming a third opening through said insulation film; and doping an impurity of the one conductivity type into said selected portion of the semiconductor layer of the opposite conductivity type through said third opening in an oxidizing atmosphere thereby forming a second region of the one conductivity type in said semiconductor layer of the opposite conductivity type.
Claim 6
Dependent Claim
258 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 3 wherein the doping step for forming said first region of the one conductivity type includes the steps of applying a silicon nitride film on the selected portions of said semiconductor layer of the opposite conductivity type which are exposed through said first and second openings and on said insulation film, forming a first silicon oxide film incorporated with an impurity of the one conductivity type on said silicon nitride film; removing with an etching solution said silicon oxide film and said silicon nitride film except the portion of said silicon nitride film and the portion of said silicon oxide film which overlies said second opening, thereby exposing said first opening; removing the remaining portion of said silicon oxide film with an etching solution; applying a second silicon oxide film incorporated with an impurity of the one conductivity type on said portion of said silicon nitride film exposed as a result of the removal of said silicon oxide film, on the portion of said semiconductor layer of the opposite conductivity type which is exposed by said first opening and on said insulation film; diffusing said impurity of the one conductivity type contained in said second silicon oxide film into said semiconductor layer of the opposite conductivity type through said first opening in a high temperature nonoxidizing atmosphere; and removing with an etching solution said second silicon oxide film and said silicon nitride film for exposing again said first and second openings through said insulation film.
Claim 7
Dependent Claim
41 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 3 wherein said first opening is formed in an annular configuration and said second and third openings are formed within the area circumscribed by said first annular opening.
Claim 8
Dependent Claim
51 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 3 wherein said first opening is formed in a grid shape thereby dividing said insulation film into a plurality of sections and said second and third openings are formed within each of said sections of said insulation film.
Claim 9
Dependent Claim
57 words
The method of manufacturing an integrated injection logic semiconductor device according to claim 3 which further includes the steps of reopening said first, second and third openings and forming electrode films on said first and second regions of the opposite conductivity type and on said second region of the one conductivity type region through the respective openings.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-23 | 1982-10-23 | 1983-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-23 | 1986-10-23 | 1987-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-23 | 1990-10-23 | 1991-04-24 | $7700.00 | Window Closed / Lapsed |