US4148016A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital to analog and analog to digital converters using CCD ramp generator
Assignee: Thales SA
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Filing: 1976-06-22
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Granted: 1979-04-03
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Expires: 1996-06-22
Abstract
Abstract The invention relates to ramp generators by which it is possible to obtain an electrical voltage which represents a ramp of a required form in dependence upon a given parameter. The invention comprises using a charge transfer device in which the charge transferred is measured in dependence upon a parameter associated with the weighting of the electrodes of the device. This weighting is fixed according to the required form of the ramp.
Inventors
- 👤 Etienne Alizon
- 👤 Jean E. Picquendar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:49
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/462; H10D44/466; H03; H03K; H03K4/00; H03K4/02; H03K4/023; H03M; H03M1/00; H03M1/004; H03M1/008
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
142 words
A digital-analog converter for converting a digital signal consisting of n bits into an analog signal, which comprises: means for counting an external clock signal composed of pulses, and delivering a stop signal when the count obtained is equal to the value of said digital signal; a charge coupled device comprising a plurality of cells weighted according to a given conversion law; means for injecting into said charge-coupled device at least one charge when said counting means is actuated; means for displacing, under the control of said external clock signal, said charge along said charge-coupled device under said weighted cells; means for measuring weighted signals induced into said weighted cells during the displacement of said charge, and providing a ramp signal; and a sample-and-hold circuit for sampling said ramp signal under the control of said stop signal, and delivering said analog signal.
Claim 2
Dependent Claim
142 words
A digital-analog converter for converting a digital signal consisting of n bits into an analog signal, which comprises: means for counting an external clock signal composed of pulses, and delivering a stop signal when the count obtained is equal to the value of said digital signal; a charge coupled device comprising a plurality of cells weighted according to a given conversion law; means for injecting into said charge-coupled device at least one charge when said counting means is actuated; means for displacing, under the control of said external clock signal, said charge along said charge-coupled device under said weighted cells; means for measuring weighted signals induced into said weighted cells during the displacement of said charge, and providing a ramp signal; and a sample-and-hold circuit for sampling said ramp signal under the control of said stop signal, and delivering said analog signal.
Claim 3
Dependent Claim
27 words
A digital-analog converter as claimed in claim 1, further comprising means for controlling the actuation of said counting means under the control of an external validation signal.
Claim 4
Dependent Claim
25 words
A digital-analog converter as claimed in claim 2, wherein said injecting means inject one charge during each one of said pulses of the clock signal.
Claim 5
Dependent Claim
51 words
A digital-analog converter as claimed in claim 3, further comprising means for transcoding n-1 bits of said digital signal into a transcoded signal, and means for inverting said analog signal under the control of the last other bit of said digital signal; said transcoded signal being applied to said counting means.
Claim 6
Dependent Claim
137 words
An analog-digital converter to converting an analog signal into a digital signal consisting of n bits, which comprises: a sample-and-hold circuit for sampling said analog signal, and providing a sample signal; a charge-coupled device comprising a plurality of cells weighted according to a given conversion law; means for injecting into said charge-coupled device at least one charge; means for displacing, under the control of an external clock signal composed of pulses, said charge along said charge-coupled device under said weighted cells; means for measuring weighted signals induced into said weighted cells during the displacement of said charges, and providing a ramp signal; means for comparing said coupled signal and said ramp signal, and delivering a validation signal; and means for counting said external clock signal, and delivering said digital signal under the control of said validation signal.
Claim 7
Dependent Claim
137 words
An analog-digital converter to converting an analog signal into a digital signal consisting of n bits, which comprises: a sample-and-hold circuit for sampling said analog signal, and providing a sample signal; a charge-coupled device comprising a plurality of cells weighted according to a given conversion law; means for injecting into said charge-coupled device at least one charge; means for displacing, under the control of an external clock signal composed of pulses, said charge along said charge-coupled device under said weighted cells; means for measuring weighted signals induced into said weighted cells during the displacement of said charges, and providing a ramp signal; means for comparing said coupled signal and said ramp signal, and delivering a validation signal; and means for counting said external clock signal, and delivering said digital signal under the control of said validation signal.
Claim 8
Dependent Claim
39 words
An analog-digital converter as claimed in claim 5, further comprising means for controlling, under the control of an external sampling signal, the actuation of said sample-and-hold circuit and of said injecting means, and the resetting of said counting means.
Claim 9
Dependent Claim
25 words
An analog-digital converter as claimed in claim 6, wherein said injecting means inject one charge during each one of said pulses of the clock signal.
Claim 10
Dependent Claim
59 words
An analog-digital converter as claimed in claim 7, further comprising means for inverting said analog signal into an inverted analog signal under the control of one of said n bits of the digital signal, and means for transcoding the other n-1 bits of said digital signal into a transcoded signal; said inverted signal being applied to said sample-and-hold circuit.
References Cited (Backward Citations)
US3313922A
Cited
US3281828A
Cited
US3408595A
Cited
US3419784A
Cited
US3597693A
Cited
US3573802A
Cited
US3750142A
Cited
US3819958A
Cited
US3942035A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-02 | 1982-10-02 | 1983-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-02 | 1986-10-02 | 1987-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-02 | 1990-10-02 | 1991-04-03 | $7700.00 | Window Closed / Lapsed |