US3573802A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar analog-to-digital feedback encoder utilizing a reversible shift register
Assignee: Fujitsu Ltd
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Filing: 1969-03-06
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Granted: 1971-04-06
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Expires: 1989-03-06
Abstract
Abstract In a nonlinear coder, a weighing resistance network for linear encoding is controlled in accordance with the nonlinear characteristic by selection of the weighing resistance via a reversible shift register.
Inventors
- 👤 Masao Kawashima
- 👤 Shigehiko Hinoshita
- 👤 Shunroku Sasaki
- 👤 Shoichi Kurita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:50
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/42
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
182 words
A nonlinear coder for piecewise lineAr compression encoding of input signals, comprising: input means for providing input signals; sign discriminating means connected to said input means for determining the sign of said input signals; full wave rectifying means connected to said input means for rectifying said input signals; network means for providing a comparison level signal; gate and memory means connected to said network means for driving said network means; comparing means; coupling means coupled between said network means and said rectifying means and said comparing means for supplying the rectified signals and the comparison level signal to said comparing means, said comparing means comparing the level of said rectified signals with said comparison level; control means connected to said comparing means for providing a control signal in accordance with the output of said comparing means; reversible shift register means connected between said control means and said gate and memory means for controlling said gate and memory means in accordance with said control signal; and output means coupled to said sign discriminating means and said comparing means for providing an output pulse.
Claim 2
Dependent Claim
182 words
A nonlinear coder for piecewise lineAr compression encoding of input signals, comprising: input means for providing input signals; sign discriminating means connected to said input means for determining the sign of said input signals; full wave rectifying means connected to said input means for rectifying said input signals; network means for providing a comparison level signal; gate and memory means connected to said network means for driving said network means; comparing means; coupling means coupled between said network means and said rectifying means and said comparing means for supplying the rectified signals and the comparison level signal to said comparing means, said comparing means comparing the level of said rectified signals with said comparison level; control means connected to said comparing means for providing a control signal in accordance with the output of said comparing means; reversible shift register means connected between said control means and said gate and memory means for controlling said gate and memory means in accordance with said control signal; and output means coupled to said sign discriminating means and said comparing means for providing an output pulse.
Claim 3
Dependent Claim
25 words
A nonlinear coder as claimed in claim 1, wherein said sign discriminating means comprises a first comparator and said comparing means comprises a second comparator.
Claim 4
Dependent Claim
17 words
A nonlinear coder as claimed in claim 1, wherein said network means comprises a linear resistance network.
Claim 5
Dependent Claim
47 words
A nonlinear coder as claimed in claim 1, wherein said output means comprises a pair of AND gates, one of said AND gates having an input connected to said comparing means and another input coupled to said sign discriminating means via the other of said AND gates.
Claim 6
Dependent Claim
21 words
A nonlinear coder as claimed in claim 1, wherein said control means controls said reversible shift register means for logarithmic compression.
Claim 7
Dependent Claim
21 words
A nonlinear coder as claimed in claim 1, wherein said control means controls said reversible shift register means for hyperbolic compression.
Claim 8
Dependent Claim
33 words
A nonlinear coder as claimed in claim 4, wherein said network means comprises a linear resistance network, said sign discriminating means comprises a first comparator and said comparing means comprises a second comparator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |