Single ramp analog to digital converter with feedback

Claim 2

An analog to digital converter for providing a digital representation of the amplitude of an unknown analog input voltage, having ramp generating means for generating a linearly increasing ramp voltage starting from a first predetermined voltage level, comprising: a. input means, including switching means, for selectively receiving a reference voltage and for selectively receiving the unknown analog input voltage; b. comparator means connected to the input means for selectively comparing the amplitude of the ramp voltage with the reference voltage or with the unknown voltage and for producing a timing gate signal starting at a specified time relative to the start of the linear increase of the ramp voltage and stopping when the ramp voltage equals the reference voltage or the unknown voltage; c. variable frequency pulse generating means for providing a series of electronic pulses; d. counting means having a comparison output, for counting the pulses provided by the pulse generating means, responsive to the comparator means to count only during the timing gate signal; e. control means connected to the input means for causing the switching means to switch to the reference voltage to provide a calibration cycle and to switch to the unknown voltage to provide a measure cycle; and f. error correction means responsive to the control means to be activated during the calibraTion cycle, connected to the comparison output of the counting means, for comparing the number of pulses counted by the counting means with a predetermined number and for increasing or decreasing the repetition rate of the pulse generating means when the count is less than, or more than the predetermined number, respectively.

Claim 3

The converter of claim 1 wherein the control means are operatively connected to the ramp generating means to return the ramp voltage to the first predetermined voltage level after a calibration or measure cycle and connected to the counting means to clear the counting means after a calibration or measure cycle.

Claim 4

The converter of claim 2 further comprising: g. polarity switching means, for receiving the unknown voltage, connected to the input means and the control means, for determining the polarity of the unknown voltage with respect to converter ground voltage and effectively reversing the polarity if it is negative.

Claim 5

The converter of claim 2 wherein the comparator means further comprise: b. i. a first differential amplifier having one input from the ramp generating means and another input from converter ground voltage to cause the first differential amplifier to be activated when the ramp voltage reaches converter ground voltage; ii. A second differential amplifier having one input from the ramp generating means and another input from the switching means of the input means, to cause the second differential amplifier to be activated until the ramp voltages reaches either the reference voltage during a calibration cycle, or the unknown voltage during a measure cycle, when the second differential amplifier becomes deactivated; iii. a first gate having an input from each of the first differential amplifier and the second differential amplifier, to cause the gate to be activated from the time of the activation of the first differential amplifier to the time of the deactivation of the second differential amplifier, producing a timing gate signal at its output; and iv. a second gate having an input from the first gate and from the pulse generating means and having an output to the counting means, to permit pulses from the pulse generating means to pass to the counting means during the timing gate signal.

Claim 6

The converter of claim 3 wherein the comparator means further comprise: b. i. a first differenial amplifier having one input from the ramp generating means and another input from converter ground voltage to cause the first differential amplifier to be activated when the ramp voltage reaches converter ground voltage; ii. a second differential amplifier having one input from the ramp generating means and another input from the switching means of the input means, to cause the second differential amplifier to be activated until the ramp voltage reaches either the reference voltage during a calibration cycle, or the unknown voltage during a measure cycle, when the second differential amplifier becomes deactivated; iii. a first gate having an input from each of the first differential amplifier and the second differential amplifier, to cause the gate to be activated from the time of the activation of the first differential amplifier to the time of the deactivation of the second differential amplifier, producing a timing gate signal at its output; and iv. a second gate having an input from the first gate and from the pulse generating means and having an output to the counting means, to permit pulses from the pulse generating means to pass to the counting means during the timing gate signal.

Claim 7

The converter of claim 4 wherein the control means further comprise: e. i. an oscillatr, for providing timing to the converter; ii. first, second and third flip-flops with the first flip-flop having the oscillator output as an input and connected to divide the oscillator frequency by two, the second flip-flop connected to the first flip-flop to divide the once-divided frequency by two, and the third flip-flop connected to the second flip-flop to divide the twice-divided frequency by two; iii. first and second AND circuits, the first AND circuit having a first input from the Q output of the first flip-flop, a second input from the Q output of the second flip-flop and a third input from the Q output of the third flip-flop to produce a reset signal on its output for resetting the counting means, and the second AND circuit having a first input from the Q output of the first flip-flop, the second input from the Q output of the second flip-flop and a third input from the Q output of the third flip-flop; iv. a fourth flip-flop having an input from the first AND circuit for producing a calibration-measure signal on its Q output which is connected to the switching means of the input means to cause the switching means to switch alternately between the reference voltage and the unknown voltage; and v. a third AND circuit having the Q output of the fourth flip-flop as an input and the output of the second AND circuit as another input, to produce an error correction activating signal during the calibration cycle, on its output which is connected to the error correction means.

Claim 8

The converter of claim 5 wherein the control means further comprise: e. i. an oscillator, for providing timing to the converter; ii. first, second and third flip-flops with the first flip-flop having the oscillator output as an input and connected to divide the oscillator frequency by two, the second flip-flop connected to the first flip-flop to divide the once-divided frequency by two, and the third flip-flop connected to the second flip-flop to divide the twice-divided frequency by two; iii. first and second AND circuits, the first AND circuit having a first input from the Q output of the first flip-flop, a second input from the Q output of the second flip-flop and a third input from the Q output of the third flip-flop to produce a reset signal on its output for resetting the counting means, and the second AND circuit having a first input from the Q output of the first flip-flop, the second input from the Q output of the second flip-flop and a third input from the Q output of the third flip-flop; iv. a fourth flip-flop having an input from the first AND circuit for producing a calibration-measure signal on its Q output which is connected to the switching means of the input means to cause the switching means to switch alternately between the reference voltage and the unknown voltage; v. a third AND circuit having the Q output of the fourth flip-flop as an input and the output of the second AND circuit as another input, to produce an error correction activating signal during the calibration cycle, on its output which is connected to the error correction means; and vi. a fourth AND circuit having one input from the second AND circuit and the Q output of the fourth flip-flop as another input and having an output connected to the polarity detecting means for producing a signal only during the measure cycle.

Claim 9

The converter of claim 7 wherein the counting means further comprise a binary counter having an input from the second gate of the comparator means and having a reset input from the first AND circuit of the control means, and having a comparison output from the most significant bit.

Claim 10

The converter of claim 8 wherein the error correction means further comprise: f. i. first and second gates, each having as one input the error correction activating signal from the third AND circuit of the control means, the other input to the first gate being the most significant bit output of the counter; ii. an inverter, having the most significant bit output of the counter as its input, its output serving as the other input to the second gate; and iii. an operational amplifier, having as its inputs the outputs of the first and second gates respectively and having its output connected to the input of the variable frequency pulse generating means.

Claim 11

The converter of claim 9 wherein the polarity switching means further comprise: g. i. a fifth flip-flop having the timing gate signal from the first gate of the comparator means as an input; ii. a sixth flip-flop connected to follow the state of the fifth flip-flop when its input receives the signal from the fourth AND circuit of the control means; and iii. an electromechanical switch having a coil connected to the output of the sixth flip-flop to be activated by a change of state of the sixth flip-flop and having a first and a second movable contact member, the pivot end of the first member being connected to converter ground and the pivot end of the second member being connected to the switching means of the input means, the first member being connected at its movable end to the common terminal in a first position and the second member being connected to the unknown voltage terminal in the first position, the first member being connected at its movable end to the unknown voltage terminal in a second position, and the second member being connected at its movable end to the common terminal in the second position, the members being activated to move between the first and second positions and the second and first positions whenever the coil is activated so that in the second position a negative voltage applied to the unknown voltage terminal will cause the unknown voltage ground applied at the common terminal to appear positive with respect to the converter ground.

Claim 12

An analog to digital converter for providing a digital representation of the amplitude of an unknown analog input voltage, having ramp generating means for generating a linearly increasing ramp voltage starting from a first predetermined voltage level, comprising: a. input means, including switching means, for selectively receiving a reference voltage and for selectively receiving the unknown analog input voltage; b. comparator means connected to the input means for selectively comparing the amplitude of the ramp voltage with the reference voltage or with the unknown voltage and for producing a timing gate signal starting at a specified time relative to the start of the linear increase of the ramp voltage and stopping when the ramp voltage equals the reference voltage or the unknown voltage; c. fixed frequency pulse generating means for providing a series of electronic pulses; d. counting means having a comparison output, for counting the pulses provided by the pulse generating means, responsive to the comparator means to count only during the timing gate signal; e. control means connected to the input means for causing the switching means to switch to the reference voltage to provide a calibration cycle and to switch to the unknown voltage to provide a measure cycle; and f. error correction means responsive to the control means to be activated during the calibration cycle, connected to the comparison output of the counting means for comparing the number of pulses counted by the counting means with a predetermined number and for decreasing or increasing the rate of rise of the ramp voltage when the count is less than, or more than the predetermined number, respectively.

Claim 13

An analog to digital converter for providing a digital representation of the amplitude of an unknown analog input voltage, having ramp generating means for generating a linearly increasing ramp voltage starting from a first predetermined voltage level, comprising: a. input means, including switching means, for selectively receiving a reference voltage and for selectively receiving the unknown analog input voltage; b. comparator means connected to the input means for selectively comparing the amplitude of the ramp voltage with the reference voltage or with the unknown voltage and for producing a timing gate signal starting at a specified time relative to the start of the linear increase of the ramp voltage and stopping when the ramp voltage equals the reference voltage or the unknown voltage; c. fixed frequency pulse generating means for providing a series of electronic pulses; d. counting means having a comparison output, for counting the pulses provided by the pulse generating means, responsive to the comparator means to count only during the timing gate signal; e. control means connected to the input means for causing the switching means to switch to the reference voltage to provide a calibration cycle and to switch to the unknown voltage to provide a measure cycle; and f. error correction means responsive to the control means to be activated during the calibration cycle, connected to the comparison output of the counting means for comparing the number of pulses counted by the counting means with a predetermined number and for decreasing or increasing the rate of rise of the ramp voltage when the count is less than, or more than the predetermined number, respectively.

Claim 14

The converter of claim 11 wherein the control means are operatively connected to the ramp generating means to return the ramp voltage to the first predetermined voltage level after a calibration or measure cycle and connected to the counting means to clear the counting means after a calibration or measure cycle.

Claim 15

The converter of claim 12 further comprising: g. polarity switching means, for receiving the unknown voltage, connected to the input means and the control means, for determining the polarity of the unknown vOltage with respect to converter ground voltage and effectively reversing the polarity if it is negative.

Claim 16

The converter of claim 12 wherein the comparator means further comprise: b. i. a first differential amplifier having one input from the ramp generating means and another input from converter ground voltage to cause the first differential amplifier to be activated when the ramp voltage reaches converter ground voltage: ii. a second differential amplifier having one input from the ramp generating means and another input from the switching means of the input means, to cause the second differential amplifier to be activated until the ramp voltage reaches either the reference voltage during a calibration cycle, or the unknown voltage during a measure cycle, when the second differential amplifier becomes deactivated; iii. a first gate hAving an input from each of the first differential amplifier and the second differential amplifier, to cause the gate to be activated from the time of the activation of the first differential amplifier to the time of the deactivation of the second differential amplifier, producing a timing gate signal at its output; and iv. a second gate having an input from the first gate and from the pulse generating means and having an output to the counting means, to permit pulses from the pulse generating means to pass to the counting means during the timing gate signal.

Claim 17

The converter of claim 13 wherein the comparator means further comprise: b. i. a first differential amplifier having one input from the ramp generating means and another input from converter ground voltage to cause the first differential amplifier to be activated when the ramp voltage reaches converter ground voltage; ii. a second differential amplifier having one input from the ramp generating means and another input from the switching means of the input means, to cause the second differential amplifier to be activated until the ramp voltage reaches either the reference voltage during a calibration cycle, or the unknown voltage during a measure cycle, when the second differential amplifier becomes deactivated; iii. a first gate having an input from each of the first differential amplifier and the second differential amplifier, to cause the gate to be activated from the time of the activation of the first differential amplifier to the time of the deactivation of the second differential amplifier, producing a timing gate signal at its output; and iv. a second gate having an input from the first gate and from the pulse generating means and having an output to the counting means, to permit pulses from the pulse generating means to pass to the counting means during the timing gate signal.

Claim 18

The converter of claim 14 wherein the control means further comprise: e. i. an oscillator, for providing timing to the converter; ii. first, second and third flip-flops with the first flip-flop having the oscillator output as an input and connectzd to divide the oscillator frequency by two, the second flip-flop connected to the first flip-flop to divide the once-divided frequency by two, and the third flip-flop connected to the second flip-flop to divide the twice-divided frequency by two; iii. first and second AND circuits, the first AND circuit having a first input from the Q output of the first flip-flop, a second input from the Q output of the second flip-flop and a third input from the Q output of the third flip-flop to produce a reset signal on its output for resetting the counting means, and the second AND circuit having a first input from the Q output of the first flip-flop, the second input from the Q output of the second flip-flop and a third input from the Q output of the third flip-flop; iv. a fourth flip-flop having an input from the first AND circuit for producing a calibration-measure signal on its Q output which is connected to the switching means of the input means to cause the switching means to switch alternately between the reference voltage and the unknown voltage; and v. a third AND circuit having the Q output of the fourth flip-flop as an input, the output of the second AND circuit as another input and having the comparison output of the counting means as a third input, to produce an error correction activating signal during the calibration cycle on its output which is connected to the error correction means.

Claim 19

The converter of claim 16 wherein the control means further comprise: e. i. an oscillator, for providing timing to the converter; ii. first, second and third flip-flops with the first flip-flop having the oscillator output as an input and connected to divide the oscillator frequency by two, the second flip-flop connected to the first flip-flop to divide the once-divided frequency by two, and the third flip-flop connected to the second flip-flop to divide the twice-divided frequency by two; iii. first and second AND circuits, the first AND circuit having a first input from the Q output of the first flip-flop, a second input from the Q output of the second flip-flop and a third input from the Q output of the third flip-flop to produce a reset signal on its output for resetting the counting means, and the second AND circuit having a first input from the Q output of the first flip-flop the second input from the Q output of the second flip-flop and a third input from the Q output of the third fiP-flOp; iv. a fourth flip-flop having an input from the first AND circuit for producing a calibration-measure signal on its Q output which is connected to the switching means of the input means to cause the switching means to switch alternately between the reference voltage and the unknown voltage; v. a third AND circuit having the Q output of the fourth flip-flop as an input, the output of the second AND circuit as anOther input and having the comparison output of the counting means as a third input, to produce an error correction activating signal during the calibration cycle on its output which is connected to the error correction means; and vi, a fourth AND circuit having one input from the second AND circuit and the Q output of the fourth flip-flop another input and having an output connected to the polarity detecting means for producing a signal only during the measure cycle.

Claim 20

The converter of claim 17 wherein the counting means further comprises a binary counter having an input from the second gate of the comparator means and having a reset input from the first AND circuit of the control means, and having a comparison output from the most significant bit.

Claim 21

The converter of claim 18 wherein the error correction means further comprise: f. i. an operational amplitude having one input connected to converter ground and having the other input connected to the output of the third AND circuit of the control means to receive the error correction activating signal, and having an output connected to the ramp generating means.

Claim 22

The converter of claim 19 wherein the polarity switching means further comprise: g. i. a fifth flip-flop having the timing gate signal from the first gate of the comparator means as an input; ii. a sixth flip-flop connected to follow the state of the fifth flip-flop when its input receIves the signal from the fourth AND circuit of the control means; and iii. an electromechanical switch having a coil connected to the output of the sixth flip-flop to be activated by a change of state of the sixth flip-flop and having a first and a second movable contact member, the pivot end of the first member being connected to converter ground and the pivot end of the second member being connected to the switching means of the input means, the first member being connected at its movable end to the commOn terminal in a first position and the second member being connected to the unknown voltage terminal in the first position, the first member being connected at its movable end to the unknown voltage terminal in a second position, and the second member being connected at its movable end to the common terminal in the second position, the members being activated to move between the first and second positions and the second and first positions whenever the coil is activated so that in the second position a negative voltage applied to the unknown voltage terminal will cause the unknown voltage ground applied at the common terminal to appear positive with respect to the converter ground.

Claim 25

The method of claim 21, after step h, further comprising the steps of: l. determining the polarity of the unknown signal voltage; and m. inverting the unknown signal voltage if it is negative.

Claim 26

The method of claim 22 further comprising the step of: n. displaying the count as a number.

Claim 27

The method of claim 23 further comprising the steps of: o. dropping the ramp voltage to the first predetermined level; and p. starting the linear rise and repeating steps a through o as desired.

Claim 28

The method of claim 24 wherein the first and second predetermined levels are the same.

Claim 29

The method of claim 24 wherein the first predetermined level is a negative voltage and the second predetermined level is zero volts.

Claim 32

The method of claim 27, after step h, further comprising the steps of: l. determining the polarity of the unknown signal voltage; and m. inverting the unknown signal voltage if it is negative.

Claim 33

The method of claim 28 further comprising the step of: n. displaying the count as a number.

Claim 34

The method of claim 29 further comprising the steps of: o. dropping the ramp voltage to the first predetermined level; and p. starting the linear rise and repeating steps a through o as desired.

Claim 35

The method of claim 30 wherein the first and second predetermined levels are the same.

Claim 36

The method of claim 31 wherein the first predetermined level is a negative voltage and the second predetermined level is zero volts.