Low forward voltage drop semiconductor device having polycrystalline layers of different resistivity

Claim 2

A semiconductor device having a low forward voltage comprising: a semiconductor substrate including a first single-crystal layer of one conductivity type, a second single-crystal layer of the one conductivity type, adjoining said first single-crystal layer and having a higher resistivity than said first single-crystal layer, and a third single-crystal layer of the opposite conductivity type, adjoining said second single-crystal layer to form a P-N junction with said second single-crystal layer; a first polycrystalline layer of the opposite conductivity type having a resistivity of at least 0.05 Ω-cm, in direct contact with said third single-crystal layer; a second polycrystalline layer of the opposite conductivity layer superposed on and in direct contact with said first polycrystalline layer, said second polycrystalline layer having a resistivity lower than that of said first polycrystalline layer; a first main electrode in low resistance contact with said first single-crystal layer; and a second main electrode in low resistance contact with said second polycrystalline layer; said third single-crystal layer being formed by diffusing from said first polycrystalline layer an impurity determining the opposite conductivity type during the formation of said first and second polycrystalline layers, having a total impurity quantity of 1 × 10 10 to 2 × 10 15 atoms/cm 2 and a thickness smaller than that of said second single-crystal layer.

Claim 3

The semiconductor device according to claim 1, wherein said polycrystalline layer is constructed of a first polycrystalline layer part adjacent to said third single-crystal layer and a second polycrystalline layer part adjacent to said first polycrystalline layer part, said first polycrystalline layer part having a thickness of 0.1 to 30 μm and a resistivity of 0.05 to 250Ω-cm, said second polycrystalline layer part having a resistivity of at most 0.05 Ω-cm, and wherein the sum of the thicknesses of said first and second polycrystalline layer parts is at least 2 μm.

Claim 4

The semiconductor device according to claim 1, wherein said first polycrystalline layer has a thickness of 0.1 to 30 μm and a resistivity of 0.05 to 250Ω-cm, and the resistivity of said second polycrystalline layer is, at most, 0.05Ω-cm, and the total thickness of said first and second polycrystalline layers is at least 2 μm.

Claim 5

A semiconductor device according to claim 1 wherein said second single-crystal layer has a thickness of at most 30 μm.

Claim 6

A semiconductor device according to claim 1 wherein said first polycrystalline layer has a thickness of 0.1 to 30 Ωm and a resistivity of 0.05 to 250Ω-cm, and said second polycrystalline layer has a resistivity of at most 0.05Ω-cm.

Claim 7

A semiconductor device according to claim 1 wherein the sum of the thicknesses of said first and second polycrystalline is at least 2 μm.

Claim 8

A semiconductor device according to claim 1 wherein the sum of the thicknesses of said second and third single-crystal layers are at most 400 μm.

Claim 9

A semiconductor device having a low forward voltage comprising: a semiconductor substrate including a first single-crystal layer of one conductivity type, a second single-crystal layer of the opposite conductivity type adjoining said first single-crystal layer to form a first P-N junction therebetween, said second single-crystal layer having a resistivity higher than that of said first single-crystal layer, a third single-crystal layer of the one conductivity type, adjoining said second single-crystal layer to form a second P-N junction therebetween, and a fourth single-crystal layer of the opposite conductivity type, adjoining said third single-crystal layer to form a third P-N junction therebetween, said fourth single-crystal layer having a resistivity lower than that of said third single-crystal layer; a first polycrystalline layer of the opposite conductivity type having a resistivity of at least 0.05Ω-cm, in direct contact with said fourth single-crystal layer; a second polycrystalline layer of the opposite conductivity type, superposed on and in direct contact with said first polycrystalline layer, said second polycrystalline layer having a resistivity lower than that of said first polycrystalline layer; a first main electrode in low resistance contact with said second polycrystalline layer; a second main electrode in low resistance contact with said first single-crystal layer; and a control electrode in low resistance contact with one of said second and third single-crystal layers; said fourth single-crystal layer being formed by diffusing from said first polycrystalline layer an impurity determining the opposite conductivity during the formation of said first and second polycrystalline layers, and having a total impurity quantity of 1 × 10 10 to 2 × 10 15 atoms/cm 2 and a thickness smaller than that of said third single-crystal layer.

Claim 10

A semiconductor device having a low forward voltage comprising: a semiconductor substrate including a first single-crystal layer of one conductivity type, a second single-crystal layer of the opposite conductivity type adjoining said first single-crystal layer to form a first P-N junction therebetween, said second single-crystal layer having a resistivity higher than that of said first single-crystal layer, a third single-crystal layer of the one conductivity type, adjoining said second single-crystal layer to form a second P-N junction therebetween, and a fourth single-crystal layer of the opposite conductivity type, adjoining said third single-crystal layer to form a third P-N junction therebetween, said fourth single-crystal layer having a resistivity lower than that of said third single-crystal layer; a first polycrystalline layer of the opposite conductivity type having a resistivity of at least 0.05Ω-cm, in direct contact with said fourth single-crystal layer; a second polycrystalline layer of the opposite conductivity type, superposed on and in direct contact with said first polycrystalline layer, said second polycrystalline layer having a resistivity lower than that of said first polycrystalline layer; a first main electrode in low resistance contact with said second polycrystalline layer; a second main electrode in low resistance contact with said first single-crystal layer; and a control electrode in low resistance contact with one of said second and third single-crystal layers; said fourth single-crystal layer being formed by diffusing from said first polycrystalline layer an impurity determining the opposite conductivity during the formation of said first and second polycrystalline layers, and having a total impurity quantity of 1 × 10 10 to 2 × 10 15 atoms/cm 2 and a thickness smaller than that of said third single-crystal layer.

Claim 11

The semiconductor device according to claim 8, wherein said polycrystalline layer is constructed of a first polycrystalline layer part adjacent to said fourth single-crystal layer and a second polycrystalline layer part adjacent to said first polycrystalline layer part, said first polycrystalline layer part having a thickness of 0.1 to 30 μm and a resistivity of 0.1 to 250Ω-cm, said second polycrystalline layer part having a resistivity of at most 0.1Ω-cm, and wherein the sum of the thicknesses of said first and second polycrystalline layer parts is at least 2 μm.

Claim 12

The semiconductor device according to claim 8, wherein the total thickness of said second and third single-crystal layers is, at most, 400 μm, and the total impurity quantity per unit area of said fourth single-crystal layer is less than 3 × 10 14 atoms/cm 2 .

Claim 13

The semiconductor device according to claim 10, wherein said first polycrystalline layer has a thickness of 0.1 to 30 μm and a resistivity of 0.1 to 250Ω-cm, and the resistivity of said second polycrystalline layer is, at most, 0.1Ω-cm, and the total thickness of said first and second polycrystalline layers is at least 2 μm.

Claim 14

A semiconductor device according to claim 8 wherein said second single-crystal layer has a thickness of at most 30 μm.

Claim 15

A semiconductor device according to claim 8 wherein said first polycrystalline layer has a thickness of 0.1 to 30 μm and a resistivity of 0.05 to 250Ω-cm, and said second polycrystalline layer has a resistivity of at most 0.05Ω-cm.

Claim 16

A semiconductor device according to claim 8 wherein the sum of the thicknesses of said first and second polycrystalline is at least 2 μm.

Claim 17

A semiconductor device according to claim 8 wherein the sum of the thicknesses of said second and third single cyrstal layers are at most 400 μm.

Claim 18

A semiconductor device having a low forward voltage comprising: a semiconductor substrate including a first single-crystal layer of one conductivity type, a second single-crystal layer of the one conductivity type, adjoining said first single-crystal layer and having a higher resistivity than said first single-crystal layer, and a third single-crystal layer of the opposite conductivity type, adjoining said second single-crystal layer to form a P-N junction with said single-crystal layer; a polycrystalline layer of the opposite conductivity type in direct contact with said third single-crystal layer, said polycrystalline layer having a resistivity of at least 0.05Ω-cm on the side which contacts the third single-crystal layer and a decrease in resistivity across the thickness of the polycrystalline layer; a first main electrode in low resistance contact with said first single-crystal layer; and a second main electrode in low resistance contact with said polycrystalline layer; said third single-crystal layer being formed by diffusing from said first polycrystalline layer an impurity determining the opposite conductivity type during the formation of said first and second polycrystalline layers, and having a total impurity quantity of 1 × 10 10 to 2 × 10 15 atoms/cm 2 and a thickness smaller than that of said second single-crystal layer.

Claim 19

A semiconductor device having a low forward voltage comprising: a semiconductor substrate including a first single-crystal layer of one conductivity type, a second single-crystal layer of the one conductivity type, adjoining said first single-crystal layer and having a higher resistivity than said first single-crystal layer, and a third single-crystal layer of the opposite conductivity type, adjoining said second single-crystal layer to form a P-N junction with said single-crystal layer; a polycrystalline layer of the opposite conductivity type in direct contact with said third single-crystal layer, said polycrystalline layer having a resistivity of at least 0.05Ω-cm on the side which contacts the third single-crystal layer and a decrease in resistivity across the thickness of the polycrystalline layer; a first main electrode in low resistance contact with said first single-crystal layer; and a second main electrode in low resistance contact with said polycrystalline layer; said third single-crystal layer being formed by diffusing from said first polycrystalline layer an impurity determining the opposite conductivity type during the formation of said first and second polycrystalline layers, and having a total impurity quantity of 1 × 10 10 to 2 × 10 15 atoms/cm 2 and a thickness smaller than that of said second single-crystal layer.

Claim 20

The semiconductor device according to claim 16, wherein the resistivity of said polycrystalline layer decreases in a linear manner through the layer.

Claim 21

The semiconductor device according to claim 16, wherein said polycrystalline layer is made up of a plurality of stacked polycrystalline layer portions each having a respectively different resistivity so as to form a polycrystalline layer having a stepwise decreasing resistivity from said single-crystal layer.

Claim 22

A semiconductor device having a low forward voltage comprising: a semiconductor substrate including a first single-crystal layer of one conductivity type, a second single-crystal layer of the opposite conductivity type adjoining said first single-crystal layer to form a first P-N junction therebetween, said second single-crystal layer having a resistivity higher than that of said first single-crystal layer, a third single-crystal layer of the one conductivity type, adjoining said second single-crystal layer to form a second P-N junction therebetween, and a fourth single-crystal layer of the opposite conductivity type, adjoining said third single-crystal layer to form a third P-N junction therebetween, said fourth single-crystal layer having a resistivity lower than that of said third single-crystal layer; a polycrystalline layer of the opposite conductivity type, in direct contact with said fourth single-crystal layer, said polycrystalline layer having a resistivity of at least 0.05Ω-cm on the side which controls the third single-crystal layer and a decrease in resistivity across the thickness of the polycrystalline layer; a first main electrode in low resistance contact with said polycrystalline layer; a second main electrode in low resistance contact with said first single-crystal layer; and a control electrode in low resistance contact with one of said second and third single-crystal layers; said fourth single-crystal layer being formed by diffusing from said first polycrystalline layer an impurity determining the opposite conductivity during the formation of said first and second polycrystalline layers, and having a total impurity quantity of 1 × 10 10 to 2 × 10 15 atoms/cm 2 and a thickness smaller than that of said third single-crystal layer.

Claim 23

A semiconductor device having a low forward voltage comprising: a semiconductor substrate including a first single-crystal layer of one conductivity type, a second single-crystal layer of the opposite conductivity type adjoining said first single-crystal layer to form a first P-N junction therebetween, said second single-crystal layer having a resistivity higher than that of said first single-crystal layer, a third single-crystal layer of the one conductivity type, adjoining said second single-crystal layer to form a second P-N junction therebetween, and a fourth single-crystal layer of the opposite conductivity type, adjoining said third single-crystal layer to form a third P-N junction therebetween, said fourth single-crystal layer having a resistivity lower than that of said third single-crystal layer; a polycrystalline layer of the opposite conductivity type, in direct contact with said fourth single-crystal layer, said polycrystalline layer having a resistivity of at least 0.05Ω-cm on the side which controls the third single-crystal layer and a decrease in resistivity across the thickness of the polycrystalline layer; a first main electrode in low resistance contact with said polycrystalline layer; a second main electrode in low resistance contact with said first single-crystal layer; and a control electrode in low resistance contact with one of said second and third single-crystal layers; said fourth single-crystal layer being formed by diffusing from said first polycrystalline layer an impurity determining the opposite conductivity during the formation of said first and second polycrystalline layers, and having a total impurity quantity of 1 × 10 10 to 2 × 10 15 atoms/cm 2 and a thickness smaller than that of said third single-crystal layer.

Claim 24

A semiconductor device according to claim 19, wherein the resistivity of said polycrystalline layer decreases in a linear manner through the layer.

Claim 25

A semiconductor device according to claim 19, wherein said polycrystalline layer is made up of a plurality of stacked polycrystalline layer portions each having a respectively different resistivity so as to form a polycrystalline layer having a stepwise decreasing resistivity from said single-crystal layer.