Patent US4144566A successfully refreshed from Google Patents.
US4144566A
Expired / Lapsed
US
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Parallel-type processor with a stack of auxiliary fast memories
Assignee: Thales SA
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Filing: 1977-08-11
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Granted: 1979-03-13
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Expires: 1997-08-11
Abstract
Abstract A parallel processor having a large number of elementary processors connected in parallel to an address bus and a control bus. Each elementary processor contains a memory and control and processing circuits to perform calculations on bits addressed in the memory and bits coming either from this memory or from a peripheral unit. Each elementary processor further contains a small capacity fast memory and the control and processing circuit contains a single storage flip-flop able to perform calculations in series on the bits extracted from the memories and/or coming from the peripheral unit. All the fast memories are parallel connected.
Inventors
- 👤 Claude Timsit
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:21
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
230 words
A parallel-type processor comprising a plurality of elementary processors connected in parallel to an address bus and to a control bus, each of said elementary processors comprising: a memory unit having an input and an output; a fast memory unit having an input and an output, said fast memory unit having a lower access time than said memory unit; and control and calculation means, comprising a single storage flip-flop, said control and calculation means being connected to the input andd output of said memory unit and to the input and output of said fast memory unit, for performing calculations on two bits extracted from the group of units formed by said memory unit, said fast memory and said storage flip-flop, the result of said calculations being written in one of the units of said group, the fast memory units of all of said elementary processors being connected together to form a stack for simultaneously translating any data from any word to the adjacent word, said stack having an input and an output and defining rows and columns of data, said parallel type processor further comprising a multiplexer having one set of outputs connected to said stack input and two sets of inputs, the first of them being connected to said stack output while the second set of inputs is connected to receive data from a souce extenal to said processor.
Claim 2
Dependent Claim
230 words
A parallel-type processor comprising a plurality of elementary processors connected in parallel to an address bus and to a control bus, each of said elementary processors comprising: a memory unit having an input and an output; a fast memory unit having an input and an output, said fast memory unit having a lower access time than said memory unit; and control and calculation means, comprising a single storage flip-flop, said control and calculation means being connected to the input andd output of said memory unit and to the input and output of said fast memory unit, for performing calculations on two bits extracted from the group of units formed by said memory unit, said fast memory and said storage flip-flop, the result of said calculations being written in one of the units of said group, the fast memory units of all of said elementary processors being connected together to form a stack for simultaneously translating any data from any word to the adjacent word, said stack having an input and an output and defining rows and columns of data, said parallel type processor further comprising a multiplexer having one set of outputs connected to said stack input and two sets of inputs, the first of them being connected to said stack output while the second set of inputs is connected to receive data from a souce extenal to said processor.
Claim 3
Dependent Claim
45 words
A parallel-type processor as claimed in claim 1 further comprising a clock generator, said generator being connected to said stack to control the shifting of data contained in the columns of said stack, under control of address signals and control signals from said control bus.
Claim 4
Dependent Claim
34 words
A parallel-type processor as claimed in claim 2 wherein each fast memory unit comprises a shift register, said processor further comprising a plurality of additional multiplexers for the reading of said shift registers. said
Claim 5
Dependent Claim
43 words
A parallel-type processor according to claim 2 wherein each fast memory unit comprises a three-state logic shift register, said processor further comprising an input/output interface for reading and writing data in said stack, said interface being connected to the rows of said stack.
Claim 6
Dependent Claim
74 words
A parallel-type processor as claimed in claim 1 wherein said fast memory units are grouped in said stack to form functional blocks of memory units, said processor further comprising an addressing circuit having an input and an output, each block in saidd stack being associated with an intermediate output of the last fast memory unit in each block and said addressing circuit to perform reading, by blocks, of the data stored in said stack.
Claim 7
Dependent Claim
35 words
A parallel-type processor according to claim 5 further comprising a multiplexor connected to said addressing circuit output for the testing of an individual bit situated in any position in the memory units comprising said stack.
Claim 8
Dependent Claim
41 words
A parallel-type proccessor according to claim 2 further comprising an internal clock circuit, said clock generator being connected both to said internal clock circuit and to the external clock circuit of any peripheral unit which may be connected to said processor.
Claim 9
Dependent Claim
34 words
A parallel-type processor according to claim 2 further comprising an analog-to-digital converter for receiving signals representative of an image, said fast memory units being connected to said converter for an analysis of said image.
Claim 10
Dependent Claim
46 words
A parallel-type processor according to claim 8 wherein said images are video images comprising modulated scanning lines and accompanied by image synchronizing pulses, said processor further comprising means for inputting and outputting the data comprising each of the lines of said image during said synchronizing pulses.
References Cited (Backward Citations)
US3106698A
Cited
US3287703A
Cited
US3312943A
Cited
US3537074A
Cited
US3544973A
Cited
US3553654A
Cited
US3597744A
Cited
US3787673A
Cited
US3815095A
Cited
US3970993A
Cited
US4065808A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |