Digital key system

Claim 2

In a security system including a key having a digital code, key reader means for receiving said key and for generating a digital signal as a result of movement of said key relative to said key reader, and comparator means for establishing an enable condition when the code signal generated by insertion of said key in said key reader matches a stored code, the improvement comprising programmable memory means for supplying said stored code to said comparator means, write circuit means for loading the code in said memory, gate means connecting said write circuit means with said code reader, said write circuit means causing the code to be loaded in said memory in response to the code signal generated upon withdrawal of said key from said code reader, said gate means normally passing said code signal to said write circuit means but adapted to inhibit passage of said code signal upon the completion of the loading of said code in said memory.

Claim 3

A digital key system including a key provided with a digital code, code reader means for receiving said key and for generating a data pulse train and a clock pulse train in response to movement of said key relative thereto, a programmable memory, write circuitry responsive to said code pulse train and said clock pulse train for programming said memory with the code formed on said key, gate means responsive to completion of the programming of the code in said memory for disabling said write circuitry to prevent subsequent programming of said memory, comparator means for comparing the code in said memory with the code generated by insertion of said key in said code reader, and means for disabling the operation of a load device in the event of a mismatch between the code on said key and the code in said memory.

Claim 4

A digital key system including a key provided with a digital code, code reader means for receiving said key and for generating a data pulse train and a clock pulse train in response to movement of said key relative thereto, a programmable memory, write circuitry responsive to said code pulse train and said clock pulse train for programming said memory with the code formed on said key, gate means responsive to completion of the programming of the code in said memory for disabling said write circuitry to prevent subsequent programming of said memory, comparator means for comparing the code in said memory with the code generated by insertion of said key in said code reader, and means for disabling the operation of a load device in the event of a mismatch between the code on said key and the code in said memory.

Claim 5

A security system including a key having a digital code, key reader means for receiving said key input generating a data pulse train and a clock pulse train in response to movement of said key relative to said reader means, a programmable read only memory, programming circuitry responsive to the data pulse train and clock pulse train generated during withdrawal of said key from said reader means for programming said memory, said key reader means generating a final clock pulse and a final data pulse upon complete withdrawal of said key from said reader means, comparator means adapted to be enabled in response to said final clock pulse and data pulse and for comparing the code of said memory with the code generated by insertion of said key in said code reader, gate means for disabling said write circuit means in response to said final clock pulse and said final data pulse, and means for disabling the operation of a load device in the event of a mismatch between the code on said key and the code in said memory.

Claim 6

A security system including a key having a digital code, key reader means for receiving said key input generating a data pulse train and a clock pulse train in response to movement of said key relative to said reader means, a programmable read only memory, programming circuitry responsive to the data pulse train and clock pulse train generated during withdrawal of said key from said reader means for programming said memory, said key reader means generating a final clock pulse and a final data pulse upon complete withdrawal of said key from said reader means, comparator means adapted to be enabled in response to said final clock pulse and data pulse and for comparing the code of said memory with the code generated by insertion of said key in said code reader, gate means for disabling said write circuit means in response to said final clock pulse and said final data pulse, and means for disabling the operation of a load device in the event of a mismatch between the code on said key and the code in said memory.