US3846756A
Expired / Lapsed
US
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Programmable sequential logic circuit
Assignee: Westinghouse Electric Corp
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Filing: 1973-06-25
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Granted: 1974-11-05
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Expires: 1993-06-25
Abstract
Abstract The modification of a programmable read only memory circuit. One or more of the outputs are supplied as feedback signals to corresponding inputs transforms the conventional read only memory circuit into a circuit capable of memory and sequential logic functions.
Inventors
- 👤 L Schmitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:40
CPC Classifications
G; G07; G07C; G07C9/00; G07C9/00174; G07C9/00658; G07C9/00674; G07C9/0069; G06; G06F; G06F7/00; G06F7/02
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
246 words
A sequential logic circuit comprising logic memory means having a plurality of inputs and outputs and including a stored program including a plurality of locations each including stored word consisting of one or more bits, digital input means connected to said inputs of said logic memory means to provide sequential entry of digital signals at said inputs, the sequential application of digital signals to said inputs of said logic memory means developing an input address comprised of a number of bits corresponding to the number of bits of said stored words, said logic memory means adapted to respond to said digital signals applied to said inputs by sequencing through one or more locations of said stored program to a location wherein the stored word exhibits a digital value equivalent to the digital value of the input address, the sequencing of an input address from one location to another causing the change of only one bit of said input address, the presence of a stored word having a digital value corresponding to the digital value of the input address causing said logic memory means to develop a digital output signal indicative thereof, and feedback means for directly connecting one or more of said outputs of said logic memory means to one or more of said inputs to apply said digital output signal to the input of said logic memory means that entered said digital signal to latch said digital signal at said input in a stable state.
Claim 2
Dependent Claim
246 words
A sequential logic circuit comprising logic memory means having a plurality of inputs and outputs and including a stored program including a plurality of locations each including stored word consisting of one or more bits, digital input means connected to said inputs of said logic memory means to provide sequential entry of digital signals at said inputs, the sequential application of digital signals to said inputs of said logic memory means developing an input address comprised of a number of bits corresponding to the number of bits of said stored words, said logic memory means adapted to respond to said digital signals applied to said inputs by sequencing through one or more locations of said stored program to a location wherein the stored word exhibits a digital value equivalent to the digital value of the input address, the sequencing of an input address from one location to another causing the change of only one bit of said input address, the presence of a stored word having a digital value corresponding to the digital value of the input address causing said logic memory means to develop a digital output signal indicative thereof, and feedback means for directly connecting one or more of said outputs of said logic memory means to one or more of said inputs to apply said digital output signal to the input of said logic memory means that entered said digital signal to latch said digital signal at said input in a stable state.
Claim 3
Dependent Claim
22 words
A sequential logic circuit as claimed in claim 1 wherein said logic memory means is comprised of a programmable read only memory.
Claim 4
Dependent Claim
71 words
A sequential logic circuit as claimed in claim 1 wherein the number of inputs of said logic memory means corresponds to the number of bits in said input addresses and each of said inputs corresponds to a bit location in said input addresses, the entry of a digital signal at one of said inputs causing said logic memory means to sequence to a new location relfecting the change in said bit.
Claim 5
Dependent Claim
68 words
A sequential logic circuit as claimed in claim 1 wherein the entry of a predetermined sequence of digital signals at said inputs of said logic memory means results in the development of feedback signals for sequentially latching each of said digital signals at the respective inputs, said logic memory means producing a control output signal when the entry of said predetermined sequence of said digital signals is completed.
Claim 6
Dependent Claim
35 words
A sequential logic circuit as claimed in claim 4 wherein the entry of a digital signal not in accord with the stored program causes said logic memory means to produce a second control output signal.
References Cited (Backward Citations)
US3569935A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-04 | 1978-05-06 | 1978-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-04 | 1982-05-06 | 1982-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-04 | 1986-05-06 | 1986-11-05 | $7700.00 | Window Closed / Lapsed |