Patent US1124347A successfully refreshed from Google Patents.
Patent US4143366A successfully refreshed from Google Patents.
US4143366A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-digital converter
Assignee: RCA Corp
•
Filing: 1977-03-23
•
Granted: 1979-03-06
•
Expires: 1997-03-23
Abstract
Abstract An analog-to-digital (A/D) converter which is capable of encoding each one of analog signal samples occurring at a high rate, such as 40 MHz (25 ns spacing), to eight digital output bits representing any one of 256 levels. Sixteen sixteen-level A/D converter sub-units each providing four binary output bits are connected in series across analog signal input terminals. A priority encoder and a multiplexer are responsive to the carry outputs of the A/D sub-units to produce four high-order digital output bits representing the rank of the sub-unit having a voltage range encompassing the voltage of an analog input signal. Gating means responsive to the four high-order output bits pass four low-order digital output bits from the one of the sixteen sub-units identified by the four high-order bits.
Inventors
- 👤 Henry G. Lewis, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:43
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/1205; H03M1/121
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
209 words
An analog-to-digital (A/D) converter, comprising analog signal input terminals, a plurality of A/D converter sub-units having analog inputs connected in series across said analog signal input terminals, each sub-units having outputs for bits representing a sub-range of analog voltages, and having a carry output for a carry signal representing an analog voltage exceeding the sub-range of the sub-unit, a priority encoder having inputs connected to carry outputs of "alternate" ones of said A/D converter sub-units, and having outputs providing all but the lowest-order one of said a multiplexer having inputs connected to carry outputs of "intermediate" ones of said A/D converter sub-units, and having an address input receptive to the output bits from said priority encoder, and having an output for the one of the inputs passed by the address input, the output providing the lowest-order one of said high-order output bits, and a plurality of multiplexers each having an address input receptive to said high-order output bits, and having inputs connected to the binary signal outputs of said A/D converter sub-units in a pattern so that output bits from the addressed one of said A/D converter sub-units are provided by a corresponding number of said multiplexers, the output bits constituting the low-order output bits of the A/D converter.
Claim 2
Dependent Claim
209 words
An analog-to-digital (A/D) converter, comprising analog signal input terminals, a plurality of A/D converter sub-units having analog inputs connected in series across said analog signal input terminals, each sub-units having outputs for bits representing a sub-range of analog voltages, and having a carry output for a carry signal representing an analog voltage exceeding the sub-range of the sub-unit, a priority encoder having inputs connected to carry outputs of "alternate" ones of said A/D converter sub-units, and having outputs providing all but the lowest-order one of said a multiplexer having inputs connected to carry outputs of "intermediate" ones of said A/D converter sub-units, and having an address input receptive to the output bits from said priority encoder, and having an output for the one of the inputs passed by the address input, the output providing the lowest-order one of said high-order output bits, and a plurality of multiplexers each having an address input receptive to said high-order output bits, and having inputs connected to the binary signal outputs of said A/D converter sub-units in a pattern so that output bits from the addressed one of said A/D converter sub-units are provided by a corresponding number of said multiplexers, the output bits constituting the low-order output bits of the A/D converter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-05 | 1982-09-04 | 1983-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-05 | 1986-09-04 | 1987-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-05 | 1990-09-04 | 1991-03-06 | $7700.00 | Window Closed / Lapsed |