Patent US4140548A successfully refreshed from Google Patents.
US4140548A
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MOS Semiconductor process utilizing a two-layer oxide forming technique
Assignee: Maruman Integrated Circuits Inc
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Filing: 1978-05-19
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Granted: 1979-02-20
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Expires: 1998-05-19
Abstract
Abstract Process for the manufacture of MOS devices by providing wafer of P-semiconductor grade silicon in a deposition reactor. The wafer is heated to a temperature of approximately 950° C. while subjecting the wafer to dry oxygen gas to produce between a very thin layer (50-250A) of silica (SiO 2 ) on a surface of the wafer. While elevating the temperature of the wafer to approximately 1000° C., the chamber is purged with nitrogen and then hydrogen gas. After an introduction of carbon dioxide gas into the chamber, silane (SiH 4 ) or dichlorosilane gas is bled into the chamber. The silane reacts with the CO 2 to deposit SiO 2 on the previously formed thermal SiO 2 . The two layers of SiO 2 may then be annealed to provide a highly coherent, defect-free gate oxide for MOS integrated circuits.
Inventors
- 👤 Jerry W. Zimmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:07
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/011; H10D64/01342; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/66; H10P14/662; H10P14/668; H10P14/6681; H10P14/6682; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
141 words
A process for the manufacture of MOS devices comprising the steps of: heating a silicon wafer to a temperature of approximately 950° C. while subjecting the wafer to dry oxygen gas to produce between 50 and 250 A of SiO 2 on a surface of the wafer; elevating the temperature of the wafer to approximately 1000° C. while purging the chamber with nitrogen and then hydrogen gas; beginning an introduction of carbon dioxide gas into the chamber; introducing silane (SiH 4 ) into the chamber which reacts with the CO 2 to deposit SiO 2 on the thermally formed SiO 2 ; terminating the flow of SiH 4 after the desired thickness of vapor deposited oxide is placed on the wafer; and introducing H 2 while reducing the temperature of the wafer to room temperature prior to removal from the chamber.
Claim 2
Dependent Claim
141 words
A process for the manufacture of MOS devices comprising the steps of: heating a silicon wafer to a temperature of approximately 950° C. while subjecting the wafer to dry oxygen gas to produce between 50 and 250 A of SiO 2 on a surface of the wafer; elevating the temperature of the wafer to approximately 1000° C. while purging the chamber with nitrogen and then hydrogen gas; beginning an introduction of carbon dioxide gas into the chamber; introducing silane (SiH 4 ) into the chamber which reacts with the CO 2 to deposit SiO 2 on the thermally formed SiO 2 ; terminating the flow of SiH 4 after the desired thickness of vapor deposited oxide is placed on the wafer; and introducing H 2 while reducing the temperature of the wafer to room temperature prior to removal from the chamber.
Claim 3
Dependent Claim
24 words
A process as recited in claim 1 wherein said annealed layers form the gate insulation and a polycrystalline silicon gate electrode is formed thereover.
Claim 4
Dependent Claim
19 words
A process as recited in claim 1 and further including the step of annealing the layers for 15-60 minutes.
Claim 5
Dependent Claim
154 words
A process for the manufacture of MOS devices comprising the steps of: providing a masked and etched wafer of P-semiconductor grade silicon in a deposition chamber; heating the wafer to a temperature of approximately 950° C. while subjecting the wafer to dry oxygen gas to produce a layer of SiO 2 on a surface of the wafer; elevating the temperature of the wafer to approximately 1000° C. while purging said chamber with nitrogen and then hydrogen gas; beginning an introduction of carbon dioxide gas into the chamber; introducing silane (SiH 4 ) into the chamber which reacts with the CO 2 to deposit approximately 350A of SiO 2 on the thermally formed SiO 2 ; terminating the flow of SiH 4 after the desired thickness of vapor deposited oxide is placed on the wafer; and introducing H 2 while reducing the temperature of the wafer to room temperature prior to removal from the chamber.
Claim 6
Dependent Claim
154 words
A process for the manufacture of MOS devices comprising the steps of: providing a masked and etched wafer of P-semiconductor grade silicon in a deposition chamber; heating the wafer to a temperature of approximately 950° C. while subjecting the wafer to dry oxygen gas to produce a layer of SiO 2 on a surface of the wafer; elevating the temperature of the wafer to approximately 1000° C. while purging said chamber with nitrogen and then hydrogen gas; beginning an introduction of carbon dioxide gas into the chamber; introducing silane (SiH 4 ) into the chamber which reacts with the CO 2 to deposit approximately 350A of SiO 2 on the thermally formed SiO 2 ; terminating the flow of SiH 4 after the desired thickness of vapor deposited oxide is placed on the wafer; and introducing H 2 while reducing the temperature of the wafer to room temperature prior to removal from the chamber.
Claim 7
Dependent Claim
20 words
A process as recited in claim 3 and further including an arsenic implant procedure to produce source and drain regions.
Claim 8
Dependent Claim
128 words
A process for the manufacture of MOS devices comprising the steps of: heating a silicon wafer to a high temperature while subjecting the wafer to dry oxygen gas to produce a layer of SiO 2 on a surface of the wafer; elevating the temperature of the wafer while purging the chamber with nitrogen and then hydrogen gas; beginning an introduction of carbon dioxide gas into the chamber; introducing silane (SiH 4 ) into the chamber which reacts with the CO 2 to deposit SiO 2 on the thermally formed SiO 2 layer; terminating the flow of SiH 4 after the desired thickness of vapor deposited oxide is placed on the wafer; and introducing H 2 while reducing the temperature of the wafer prior to removal from the chamber.
Claim 9
Dependent Claim
128 words
A process for the manufacture of MOS devices comprising the steps of: heating a silicon wafer to a high temperature while subjecting the wafer to dry oxygen gas to produce a layer of SiO 2 on a surface of the wafer; elevating the temperature of the wafer while purging the chamber with nitrogen and then hydrogen gas; beginning an introduction of carbon dioxide gas into the chamber; introducing silane (SiH 4 ) into the chamber which reacts with the CO 2 to deposit SiO 2 on the thermally formed SiO 2 layer; terminating the flow of SiH 4 after the desired thickness of vapor deposited oxide is placed on the wafer; and introducing H 2 while reducing the temperature of the wafer prior to removal from the chamber.
Claim 10
Dependent Claim
21 words
A process as recited in claim 6 and further including the step of annealing the layers for 15 to 60 minutes.
Claim 11
Dependent Claim
24 words
A process as recited in claim 7 wherein said annealed layers form the gate insulation and a polycrystalline silicon gate electrode is formed thereover.
Claim 12
Dependent Claim
20 words
A process as recited in claim 8 and further including an arsenic implant procedure to produce source and drain regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-19 | 1982-08-21 | 1983-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-19 | 1986-08-21 | 1987-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-19 | 1990-08-21 | 1991-02-20 | $7700.00 | Window Closed / Lapsed |