US4139787A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Line-addressable random-access memory decoupling apparatus
Assignee: National Semiconductor Corp
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Filing: 1977-10-11
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Granted: 1979-02-13
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Expires: 1997-10-11
Abstract
Abstract A decoupling apparatus for a charge-coupled device line-addressable random-access memory includes a series of bipolar transistors, the bases of which are connected to output lines from the CCD LARAM. The emitters of the bipolar transistors, connected together, are connected to the source of a depletion-mode MOS reset transistor and to a comparator circuit.
Inventors
- 👤 Gilbert F. Amelio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:08
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/287; H; H10; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/454
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
74 words
A decoupling circuit for decoupling a comparator circuit from signals presented on a plurality of output lines wherein said decoupling circuit comprises: a first plurality of transistors each having a first terminal connected to a different one of the output lines and each having a second terminal connected to the comparator circuit; and a second plurality of transistors each having a first terminal connected to a different one of the first plurality of transistors.
Claim 2
Dependent Claim
74 words
A decoupling circuit for decoupling a comparator circuit from signals presented on a plurality of output lines wherein said decoupling circuit comprises: a first plurality of transistors each having a first terminal connected to a different one of the output lines and each having a second terminal connected to the comparator circuit; and a second plurality of transistors each having a first terminal connected to a different one of the first plurality of transistors.
Claim 3
Dependent Claim
19 words
A decoupling circuit as in claim 1 wherein each of the first plurality of transistors is a bipolar transistor.
Claim 4
Dependent Claim
26 words
A decoupling circuit as in claim 2 wherein the first terminal of each of the bipolar transistors is connected to the base of that bipolar transistor.
Claim 5
Dependent Claim
39 words
A decoupling circuit as in claim 2 wherein the second terminal of each bipolar transistor is connected to the emitter of that bipolar transistor and the emitters of the bipolar transistors are connected together and to the comparator circuit.
Claim 6
Dependent Claim
37 words
A decoupling circuit as in claim 1 wherein the first terminal of each of the second plurality of transistors is connected to the first terminal of a different one of each of the first plurality of transistors.
Claim 7
Dependent Claim
31 words
A decoupling circuit as in claim 5 wherein each of the first plurality of transistors is a bipolar transistor and each of the second plurality of transistors is an MOS transistor.
Claim 8
Dependent Claim
50 words
A decoupling circuit as in claim 6 wherein the first terminal of each of the bipolar transistors is connected to the base of that bipolar transistor and the first terminal of each of the MOS transistors is connected to one of the source and the drain of that MOS transistor.
Claim 9
Dependent Claim
45 words
A decoupling circuit as in claim 7 wherein the second terminal of each of the bipolar transistors is connected to the emitter of that bipolar transistor, and each of the second terminals of the bipolar transistors is connected together and connected to the comparator circuit.
Claim 10
Dependent Claim
22 words
A decoupling circuit as in claim 8 wherein each of the collectors of the plurality of bipolar transistors is connected to ground.
Claim 11
Dependent Claim
41 words
A decoupling circuit as in claim 8 wherein: the base of each bipolar transistor is connected to the source of the corresponding MOS transistor, and the drains of all the corresponding MOS transistors are connected to a source of electrical signals.
Claim 12
Dependent Claim
21 words
A structure as in claim 10 wherein: the bipolar transistors are vertical pnp transistors, and the MOS transistors are depletion-mode transistors.
References Cited (Backward Citations)
US3597626A
Cited
US3764826A
Cited
US3663887A
Cited
US3714465A
Cited
US3819953A
Cited
US3904977A
Cited
US4020364A
Cited
US3983413A
Cited
US4024512A
Cited
US4084256A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-02-12 | 1982-08-14 | 1983-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-02-12 | 1986-08-14 | 1987-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-02-12 | 1990-08-14 | 1991-02-13 | $7700.00 | Window Closed / Lapsed |