US3714465A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog decision circuit
Assignee: Individual
•
Filing: 1972-01-14
•
Granted: 1973-01-30
•
Expires: 1992-01-14
Abstract
Abstract An analog decision circuit for analyzing a group of analog signals and identifying and ordering these signals according to their magnitudes. A first analog signal OR circuit identifies the largest magnitude analog signal and by means of a feedback circuit, this signal is eliminated from a second analog signal OR circuit which identifies the next largest analog signal. A second feedback circuit eliminates the second largest analog signal from the input of a third analog signal OR circuit which identifies the third largest analog signal. Similar circuitry is provided for each additional analog signal. Comparator circuits are also included to determine the separation between one largest analog signal and the next largest signal.
Inventors
- 👤 D Skrenes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:43
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/0038
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
138 words
An analog decision circuit for simultaneously identifying and ordering analog signals of a group of analog signals according to their magnitudes comprising; an analog signal OR circuit for each order, each analog signal OR circuit having inputs for simultaneously receiving said analog signals and outputs for identifying the largest analog signal and an output on which the largest analog signal will appear for said order, and a switch for each analog signal input of each order of analog signal OR circuits except the highest order connected to apply the associated analog signal to the associated input when on and connected to be switched off by the identifying output of a higher order position analog signal OR circuit having the same analog signal input when said identifying output identifies said analog signal input as being the largest analog signal.
Claim 2
Dependent Claim
138 words
An analog decision circuit for simultaneously identifying and ordering analog signals of a group of analog signals according to their magnitudes comprising; an analog signal OR circuit for each order, each analog signal OR circuit having inputs for simultaneously receiving said analog signals and outputs for identifying the largest analog signal and an output on which the largest analog signal will appear for said order, and a switch for each analog signal input of each order of analog signal OR circuits except the highest order connected to apply the associated analog signal to the associated input when on and connected to be switched off by the identifying output of a higher order position analog signal OR circuit having the same analog signal input when said identifying output identifies said analog signal input as being the largest analog signal.
Claim 3
Dependent Claim
138 words
An analog decision circuit for simultaneously identifying and ordering analog signals of a group of analog signals according to their magnitudes comprising; an analog signal OR circuit for each order, each analog signal OR circuit having inputs for simultaneously receiving said analog signals and outputs for identifying the largest analog signal and an output on which the largest analog signal will appear for said order, and a switch for each analog signal input of each order of analog signal OR circuits except the highest order connected to apply the associated analog signal to the associated input when on and connected to be switched off by the identifying output of a higher order position analog signal OR circuit having the same analog signal input when said identifying output identifies said analog signal input as being the largest analog signal.
Claim 4
Dependent Claim
138 words
An analog decision circuit for simultaneously identifying and ordering analog signals of a group of analog signals according to their magnitudes comprising; an analog signal OR circuit for each order, each analog signal OR circuit having inputs for simultaneously receiving said analog signals and outputs for identifying the largest analog signal and an output on which the largest analog signal will appear for said order, and a switch for each analog signal input of each order of analog signal OR circuits except the highest order connected to apply the associated analog signal to the associated input when on and connected to be switched off by the identifying output of a higher order position analog signal OR circuit having the same analog signal input when said identifying output identifies said analog signal input as being the largest analog signal.
Claim 5
Dependent Claim
22 words
The analog decision circuit of claim 1 where said analog signal OR circuits have an emitter follower transistor for each analog input.
Claim 6
Dependent Claim
57 words
The analog decision circuit of claim 2 wherein the identifying outputs of each analog signal OR circuit are connected to the collectors of said emitter followers and the output for said analog circuit on which the largest analog signal for that order will appear is commonly connected to the emitters of said emitter followers of that order.
Claim 7
Dependent Claim
23 words
The analog decision circuit of claim 1 where said switches include a pair of diodes connected so that the switch is normally on.
Claim 8
Dependent Claim
75 words
The analog decision circuit of claim 3 further comprising an inverter corresponding to and connected to the collector of each transistor in each order of analog signal OR circuits and a transistor driver corresponding to and connected to each inverter in each order to be turned on when there is an output on the corresponding collector, the output of said transistor driver being connected to corresponding switches of lower orders to turn the same off.
Claim 9
Dependent Claim
33 words
The analog decision circuit of claim 1 further comprising determining means for determining the difference in magnitude between the largest analog signal for one order and the largest analog signal for another order.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |