Patent CH93370A successfully refreshed from Google Patents.
Patent US4128880A successfully refreshed from Google Patents.
US4128880A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer vector register processing
Assignee: Cray Inc
•
Filing: 1976-06-30
•
Granted: 1978-12-05
•
Expires: 1996-06-30
Abstract
Abstract Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to vector register with minimal delay, rather than memory to functional unit and return to memory with its attendant much greater start-up delays. Data may be bulk transferred between memory and some vector registers while other vector registers are involved in vector processing with one or more functional units. In vector processing elements of one or more vector registers are successively transmitted as operands to a functional unit at a rate of one per clock period, and results are transmitted from a functional unit to a receiving vector register at the same rate. In a chaining mode of operation, the elements in a result vector register become available for immediate and simultaneous transmission as operands to another functional unit. In this mode, more than one result can be obtained per clock period.
Inventors
- 👤 Seymour R. Cray, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:40
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8084; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
239 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including means for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said main memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit on successive clock periods, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, on successive clock periods following delivery of the first result from the functional unit.
Claim 2
Dependent Claim
239 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including means for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said main memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit on successive clock periods, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, on successive clock periods following delivery of the first result from the functional unit.
Claim 3
Dependent Claim
57 words
Vector processing apparatus according to claim 1 wherein said path select means and said control means are adapted for transmitting successive elements from a selected pair of any of said vector registers as operands to a functional unit and for transmitting results from the functional unit to a selected one of any of the other vector registers.
Claim 4
Dependent Claim
59 words
Vector processing apparatus according to claim 1 wherein said apparatus includes a plurality of independent segmented functional units and wherein said path select means and control means are operative in a chaining mode of operation to simultaneously transmit successive results received at one of said vector registers from a functional unit to another functional unit as successive operands therefor.
Claim 5
Dependent Claim
86 words
Vector processing apparatus according to claim 1 wherein said apparatus includes a plurality of independent segmented functional units and wherein said path select means and control means are adapted for transmitting successive elements from a first vector register as operands to a first functional unit and results from said first functional unit to a second vector register, and simultaneously transmitting successive elements from a third vector register as operands to a second functional unit and results from the second functional unit to a fourth vector register.
Claim 6
Dependent Claim
38 words
Vector processing apparatus according to claim 4 wherein said control means is operative in a chaining mode of operation so that results received from the first functional unit are simultaneously transmitted as operands to the second functional unit.
Claim 7
Dependent Claim
41 words
Vector processing apparatus according to claim 4 wherein said control means includes means for reserving a vector register involved in one vector process from involvement in another vector process and for removing the reservation upon completion of the first vector process.
Claim 8
Dependent Claim
55 words
Vector processing apparatus according to claim 6 further including means for temporarily removing the reservation of a vector register involved in receiving results in a vector operation at a time corresponding to receiption of the first result element, so as to permit use of said register as an operand register in a chained vector operation.
Claim 9
Independent Claim
156 words
The method of processing vectors in a computer having a main memory, a plurality of vector registers and at least one segmented arithmetic or logical functional unit for receiving successive inputs of operands while holding data for operations still being completed and for delivering successive operation results, comprising the steps of: intermittently transmitting data from the main computer memory to vector registers for storage as a plurality of elements of an ordered set of data; selecting from said plurality of vector registers at least one vector register to provide operands and one vector register to receive results; successively transmitting the elements of the ordered set of data from the selected operand vector register to a functional unit on successive clock periods; and successively transmitting results produced by the functional unit as elements of an ordered set to the selected result vector register on successive clock periods following delivery of the first result from the functional unit.
Claim 10
Independent Claim
156 words
The method of processing vectors in a computer having a main memory, a plurality of vector registers and at least one segmented arithmetic or logical functional unit for receiving successive inputs of operands while holding data for operations still being completed and for delivering successive operation results, comprising the steps of: intermittently transmitting data from the main computer memory to vector registers for storage as a plurality of elements of an ordered set of data; selecting from said plurality of vector registers at least one vector register to provide operands and one vector register to receive results; successively transmitting the elements of the ordered set of data from the selected operand vector register to a functional unit on successive clock periods; and successively transmitting results produced by the functional unit as elements of an ordered set to the selected result vector register on successive clock periods following delivery of the first result from the functional unit.
Claim 11
Dependent Claim
32 words
The method according to claim 8 including the further step of simultaneously transmitting result elements received at the selected result vector register to another functional unit as operands for another vector process.
Claim 12
Dependent Claim
37 words
The method according to claim 9 including the further steps of reserving a vector register involved in one vector process from involvement in another vector process, and removing the reservation upon completion of the first vector process.
Claim 13
Dependent Claim
54 words
The method according to claim 10 including the further steps of temporarily removing the reservation of a vector register involved in receiving results in a vector process at a time corresponding to reception of the first result element, and simultaneously transmitting received result elements from the register as operands in a chained vector operation.
Claim 14
Dependent Claim
23 words
The method according to claim 8 including the further step of intermittently transmitting result vectors from vector registers to the main computer memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-04 | 1982-06-05 | 1982-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-04 | 1986-06-05 | 1986-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-04 | 1990-06-05 | 1990-12-05 | $7700.00 | Window Closed / Lapsed |