US4118786A
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Integrated binary-BCD look-ahead adder
Assignee: International Business Machines Corp
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Filing: 1977-01-10
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Granted: 1978-10-03
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Expires: 1997-01-10
Abstract
Abstract An improved system for adding two numbers together. The numbers may be expressed either in binary form or in binary coded decimal form (wherein each decimal digit is represented by its equivalent four binary bits). By taking advantage of "don't care" decimal input conditions, a minimal implementation of a carry look-ahead adder which can operate upon both types of numbers is obtained.
Inventors
- 👤 Samuel R. Levine
- 👤 Shanker Singh
- 👤 Arnold Weinberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/492; G06F7/493; G06F7/494; G06F7/50; G06F7/505; G06F7/506; G06F7/508; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3832; G06F2207/3844; G06F2207/492; G06F2207/4921
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
120 words
A logic system for performing addition of two numbers, in one of a plurality of number bases, each number consisting of binary-coded representation of at least one digit, comprising: signalling means for indicating the number base being utilized; first logic means for signalling a carry C into said one digit; and second logic means responsive to said signalling means and to said first logic means for implementing sum bits Si by logically solving the equation Si = Xi C + Yi C or its logical equivalent, where Xi and Yi are predetermined logical combinations of the output of said signalling means and of Ai and Bi, where Ai and Bi are respective bits of arithmetic weight i of said digits.
Claim 2
Dependent Claim
120 words
A logic system for performing addition of two numbers, in one of a plurality of number bases, each number consisting of binary-coded representation of at least one digit, comprising: signalling means for indicating the number base being utilized; first logic means for signalling a carry C into said one digit; and second logic means responsive to said signalling means and to said first logic means for implementing sum bits Si by logically solving the equation Si = Xi C + Yi C or its logical equivalent, where Xi and Yi are predetermined logical combinations of the output of said signalling means and of Ai and Bi, where Ai and Bi are respective bits of arithmetic weight i of said digits.
Claim 3
Dependent Claim
152 words
The logic system of claim 1 wherein the digits can be expressed either in binary-coded-decimal or in hexadecimal format, and wherein: the output of said signalling means is either a signal DEC indicating decimal arithmetic or a signal DEC indicating hexadecimal arithmetic; and said second logic means includes means for logically solving the following equations or their logical equivalents: Y1 = H1 x1 = h1 y2 = h2·dec + p8·g4·h2 + g4·g2·dec + h8·h4·h1·dec + g8·dec x2 = h2·dec + p8·p4·h2 + p8·g4·p2 + g4·h2·dec + h8·h2·dec y4 = p4·g2 + p8·h4·g2 +h4·g2·dec + g4·g2·dec + h4·h2 + g8·dec x4 = p8·p4·h 2 + h4·h2·dec + h4·p2 + h4·g2 + h8·h4·dec y8 = h8·h4·g2 + h8·p4·p2 + h8·g4·dec + h8·p4·dec + h8·g4·g2·dec + g4·p2·dec x8 = h8·h4·h2 + h8·h4·g2·dec + h8·g4·dec + h8·p4·dec + h8·g4 · p2·dec + g8·dec where Pi = Ai + Bi Gi = Ai·Bi Hi = Ai Bi.
Claim 4
Independent Claim
112 words
A method for performing addition of two numbers, in one of a pluarlity of number bases, in a logic system including a plurality of logic circuits, each number consisting of a binary-coded representation of at least one digit, said method comprising: producing a first electrical signal indicating the number base being utilized; logically producing a carry signal C into said one digit; logically producing sum bits Si by logically solving the equation Si = Xi·C + Yi·C or its logical equivalent, where Xi and Yi are predetermined logical combinations of said first electrical signal and Ai and Bi, where Ai and Bi are respective bits of arithmetic weight i of said digits.
Claim 5
Independent Claim
112 words
A method for performing addition of two numbers, in one of a pluarlity of number bases, in a logic system including a plurality of logic circuits, each number consisting of a binary-coded representation of at least one digit, said method comprising: producing a first electrical signal indicating the number base being utilized; logically producing a carry signal C into said one digit; logically producing sum bits Si by logically solving the equation Si = Xi·C + Yi·C or its logical equivalent, where Xi and Yi are predetermined logical combinations of said first electrical signal and Ai and Bi, where Ai and Bi are respective bits of arithmetic weight i of said digits.
Claim 6
Dependent Claim
145 words
The method of claim 3 wherein the digits are expressed either in binary-coded-decimal or in hexadecimal format, a a signal DEC indicates decimal arithmetic, a signal DEC indicates hexadecimal arithmetic, and wherein Xi and Yi (i = 1, 2, 4, 8) are produced by logically solving the following equations or their logical equivalents: Y1 = H1 x1 = h1 y2 = h2·dec + p8·g4·h2 + g4·g2·dec + h8·h4·h2·dec + g8·dec x2 = h2·dec + p8·p4·h1 + p8·g4·p2 + g4·h2·dec + h8·h2·dec y4 = p4·g2 + p8·h4 ·g2 + h4·g2·dec + g4·g2·dec + h4·h2 + g8·dec x4 = p8·p4·h2 + h4·h2·dec + h4·p2 + h4·g2 + h8·h4·dec y8 = h8·h4·g2 + h8·p4·p2 + h8·g4·dec + h8·p4·dec + h8·g4·g2·dec + g4·p2·dec x8 = h8·h4·h2 + h8·h4·g2·dec + h8·g4·dec + h8·p4·dec + h8·g4·p2·dec + g8·dec where Pi = Ai + Bi Gi = Ai·Bi Hi = Ai Bi.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-02 | 1982-04-03 | 1982-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-02 | 1986-04-03 | 1986-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-02 | 1990-04-03 | 1990-10-03 | $7700.00 | Window Closed / Lapsed |