US4110835A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bucket brigade circuit for signal scaling
Assignee: International Business Machines Corp
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Filing: 1977-08-31
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Granted: 1978-08-29
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Expires: 1997-08-31
Abstract
Abstract A charge transfer device capacitive ratio voltage multiplication circuit has been devised which solves the problem of cumulative DC bias offset by adding a DC signal compensation branch to prevent the accumulation of DC offset potential. The circuit can be expanded to form a weighted sum of multiple inputs which does not incur any corresponding DC bias offset, by making the sum of the characteristic capacitances of each of the multiple inputs equal to the characteristic capacitance of the output portion of the charge transfer device circuit. The circuit allows arithmetic operations to be performed on input signals solely in the charge domain without the necessity of converting charge to voltage to charge, thereby avoiding losses, distortions, offsets and a reduction in dynamic range which would otherwise result.
Inventors
- 👤 James F. Dubil
- 👤 Howard N. Leighton
- 👤 Raymond J. Wilfinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:44
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/14; G06G7/16
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
185 words
In a charge transfer device, a capacitive ratio multiplier which avoids DC bias offset, comprising: a first input branch having a first characteristic capacitance, an input node and an output node, with a first signal having an information component to be multiplied and a DC bias component, being applied at its input node; an output branch having a second characteristic capacitance with its input node connected to said output node of said first input branch, the ratio of said first characteristic capacitance to said second characteristic capacitance providing an information component multiplication of said first signal as it propagates from said first input branch to said output branch; a second input branch having a third characteristic capacitance with its output node connected to said input node of said output branch, the sum of said first and third characteristic capacitances equalling said second characteristic capacitance, said second input branch having an input node with a DC bias component; whereby if the DC bias components in said first and said second input branches are equal, then they will equal the DC bias component in said output branch.
Claim 2
Dependent Claim
185 words
In a charge transfer device, a capacitive ratio multiplier which avoids DC bias offset, comprising: a first input branch having a first characteristic capacitance, an input node and an output node, with a first signal having an information component to be multiplied and a DC bias component, being applied at its input node; an output branch having a second characteristic capacitance with its input node connected to said output node of said first input branch, the ratio of said first characteristic capacitance to said second characteristic capacitance providing an information component multiplication of said first signal as it propagates from said first input branch to said output branch; a second input branch having a third characteristic capacitance with its output node connected to said input node of said output branch, the sum of said first and third characteristic capacitances equalling said second characteristic capacitance, said second input branch having an input node with a DC bias component; whereby if the DC bias components in said first and said second input branches are equal, then they will equal the DC bias component in said output branch.
Claim 3
Dependent Claim
257 words
In a charge transfer device, a circuit for performing a weighted sum of multiple inputs, comprising: a first input branch having a first characteristic capacitance, an input node and an output node, with a first signal having an information component to be multiplied and a DC bias component, being applied to said input node; an output branch having a second characteristic capacitance with its input node connected to said output node of said first input branch; a second input branch having a third characteristic capacitance, an input node and an output node, with its output node connected to said input node of said output branch, having an input node to which a DC bias component is applied; a third input branch having a fourth characteristic capacitance, an input node and an output node, with its output node connected to said input node of said output branch, with a third signal having another information component to be multiplied and a DC bias component, being applied to said input node; the ratio of said first characteristic capacitance to said second characteristic capacitance providing a multiplication for the information component of said first signal; the ratio of the third characteristic capacitance to the second characteristic capacitance providing a multiplication for the information component of said third signal; the sum of said first, third and fourth characteristic capacitances of said input branches being equal to said second characteristic capacitance of said output branch; whereby a weighted sum of said first and third information components is performed without a DC bias offset.
Claim 4
Dependent Claim
257 words
In a charge transfer device, a circuit for performing a weighted sum of multiple inputs, comprising: a first input branch having a first characteristic capacitance, an input node and an output node, with a first signal having an information component to be multiplied and a DC bias component, being applied to said input node; an output branch having a second characteristic capacitance with its input node connected to said output node of said first input branch; a second input branch having a third characteristic capacitance, an input node and an output node, with its output node connected to said input node of said output branch, having an input node to which a DC bias component is applied; a third input branch having a fourth characteristic capacitance, an input node and an output node, with its output node connected to said input node of said output branch, with a third signal having another information component to be multiplied and a DC bias component, being applied to said input node; the ratio of said first characteristic capacitance to said second characteristic capacitance providing a multiplication for the information component of said first signal; the ratio of the third characteristic capacitance to the second characteristic capacitance providing a multiplication for the information component of said third signal; the sum of said first, third and fourth characteristic capacitances of said input branches being equal to said second characteristic capacitance of said output branch; whereby a weighted sum of said first and third information components is performed without a DC bias offset.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |