Circuit for amplifying charge

Claim 2

The combination comprising: a charge transfer register having a plurality of stages, said register adapted to receive a charge signal and including means for transferring said signal from stage-to-stage along said register; a multiplicity of amplifying means spaced along said register; each amplifying means having an input coupled to a different one of said stages of said register for sensing said charge signal and having an output point for producing thereat an output signal in response to said charge signal; a common output point; and means for summing the charge signals produced at the output points of said amplifying means, including charge transfer means coupled between said output points of said amplifying means and said common output point.

Claim 3

The combination as claimed in claim 1 wherein said charge transfer register is of the bucket brigade type.

Claim 4

The combination as claimed in claim 1 wherein said charge transfer register is of the charge coupled type.

Claim 5

The combination as claimed in claim 1 wherein each one of said amplifying means is a charge amplifier which in response to a given charge signal at its input produces an increased charge signal at its output.

Claim 6

The combination as claimed in claim 1 wherein said charge transfer means of said summing means are of the bucket-brigade type.

Claim 7

The combination as claimed in claim 1 wherein said charge transfer means of said summing means are of the charge-coupled type.

Claim 8

The combination as claimed in claim 1 wherein said charge transfer means of said summing means provide different delays between said output points of said amplifying means and said common point for bringing the output signals produced at said output points into coincidence at said common point.

Claim 9

The combination as claimed in claim 1 wherein said summing means includes at least one common conductor element; wherein said charge transfer means of said summing means includes charge transfer registers connected between the outputs points of selected ones of said amplifying means and said conductor element, wherein said transfer registers of said summing means are of varying lengths to provide different delays between the selected output points and the conductor element for bringing the output signals produced at said output points into time coincidence at the conductor element; and wherein said summing means includes means coupling said conductor element to said common output point.

Claim 10

The combination as claimed in claim 1 wherein said summing means includes two conductors; wherein said charge transfer means of said summing means includes charge transfer registers connected between the output points of selected ones of every other one of said amplifying means and one of said two conductors and charge transfer registers connected between the output points of selected ones of the remaining amplifying means and the other one of said two conductors; wherein said charge transfer registers of said summing means are of varying lengths to provide different delays between the selected output points and their respective conductors for bringing the output signals produced at said output points into time coincidence at their respective conductors; and a summing amplifier coupled between said two conductors and said common point for combining the output signals of said two conductors at said common output point.

Claim 11

The combination comprising: an input point for the application thereto of input signals; and an output point for the production thereat of amplified signals; an input charge transfer register having an input terminal connected to said Input point and a plurality of output nodes; means coupled to said input register for transferring charge signals corresponding to said input signals from output node to output node along said input register; a plurality of charge amplifiers, each amplifier having an input terminal connected to a different one of said output nodes and an output terminal; and charge transfer summing means connected between each one of said output terminals of said amplifiers and said output point for delaying the signals produced at said output terminals by different amounts to bring them into time coincidence at said output point.

Claim 12

The combination comprising: an input point for the application thereto of input signals; and an output point for the production thereat of amplified signals; an input charge transfer register having an input terminal connected to said Input point and a plurality of output nodes; means coupled to said input register for transferring charge signals corresponding to said input signals from output node to output node along said input register; a plurality of charge amplifiers, each amplifier having an input terminal connected to a different one of said output nodes and an output terminal; and charge transfer summing means connected between each one of said output terminals of said amplifiers and said output point for delaying the signals produced at said output terminals by different amounts to bring them into time coincidence at said output point.

Claim 13

The combination as claimed in claim 10 wherein said charge transfer summing means includes a transfer register having a multiplicity of input nodes and an output node; and means for connecting different ones of said output terminals of said amplifying means to different ones of said input nodes of said summing register; and means coupling the output node of said summing register to said output point.