US3819954A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal level shift compensation in chargetransfer delay line circuits
Assignee: General Electric Co
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Filing: 1973-02-01
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Granted: 1974-06-25
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Expires: 1993-02-01
Abstract
Abstract Compensation for undesired shifts in the D.C. voltage level of a signal being propagated through a charge-transfer delay line is provided by compensating stages spaced at regular intervals along the delay line. The compensating stages are preferably transistors of the same type as that used in the delay line and having their source (or drain) electrodes connected to appropriate nodes along the delay line and their gate electrodes supplied from a pulsed source of voltage having controllable voltage amplitude and pulse repetition rate. The drain (or source) electrodes are grounded for shifting the D.C. voltage level in a first polarity voltage direction and are open or connected to a D.C. voltage source for shifting in the opposite polarity voltage direction.
Inventors
- 👤 W Butler
- 👤 M Barron
- 👤 B Kurz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 01:44
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
214 words
A charge-transfer delay line circuit having compensation for undesired shifts in D.C. voltage level of an analog signal being propagated through the delay line due to undesired charge loss to, or gain from, the substrate independent of the analog signal and comprising an input sampling stage for sampling an analog signal applied to an input thereof, a plurality of serially connected delay line stages wherein a first of said delay line stages has an input connected to an output of said input sampling stage, an output stage having an input connected to an output of a last of said delay line stages, and means independent of said delay line stages and the analog signal and spaced at regular intervals along said plurality of delay line stages and having only first ends connected thereto for compensating for undesired shifts in the D.C. voltage level of the sampled analog signal being propagated through the delay line stages due to undesired charge loss in the substrate on which the delay line circuit is fabricated as a result of reverse leakage current across p-n junctions in the circuit or due to charge gain in the substrate as a result of a chargepumping phenomenon, the compensation being independent of the capacitance of any fixed device in the compensating means.
Claim 2
Dependent Claim
214 words
A charge-transfer delay line circuit having compensation for undesired shifts in D.C. voltage level of an analog signal being propagated through the delay line due to undesired charge loss to, or gain from, the substrate independent of the analog signal and comprising an input sampling stage for sampling an analog signal applied to an input thereof, a plurality of serially connected delay line stages wherein a first of said delay line stages has an input connected to an output of said input sampling stage, an output stage having an input connected to an output of a last of said delay line stages, and means independent of said delay line stages and the analog signal and spaced at regular intervals along said plurality of delay line stages and having only first ends connected thereto for compensating for undesired shifts in the D.C. voltage level of the sampled analog signal being propagated through the delay line stages due to undesired charge loss in the substrate on which the delay line circuit is fabricated as a result of reverse leakage current across p-n junctions in the circuit or due to charge gain in the substrate as a result of a chargepumping phenomenon, the compensation being independent of the capacitance of any fixed device in the compensating means.
Claim 3
Dependent Claim
32 words
The charge-transfer delay line circuit set forth in claim 1 wherein said charge-transfer delay line circuit including said compensating means is a monolithic integrated circuit formed on a single integrated circuit chip.
Claim 4
Dependent Claim
81 words
The charge-transfer delay line circuit set forth in claim 1 wherein said compensating means comprise at least one electronically controlled charge-pumping device having an output connected to an associated at least one selected node along said delay line stages which defines the regular intervals, said compensating device providing a controllable compensating D.C. voltage level shift equal to, and of polarity opposite to, that of the undesired level shift which occurs in one of the regular intervals along the delay line stages.
Claim 5
Dependent Claim
81 words
The charge-transfer delay line circuit set forth in claim 1 wherein said compensating means comprise at least one electronically controlled current device having an output connected to an associated at least one selected node along said delay line stages which defines the regular intervals, said current device providing a controllable compensating D.C. voltage level shift equal to, and of polarity opposite to, that of the undesired level shift which occurs in one of the regular intervals along the delay line stages.
Claim 6
Dependent Claim
111 words
The charge-transfer delay line circuit set forth in claim 1 wherein said compensating means comprise at least one electronically controlled device having an output connected to an associated at least one selected node along said delay line stages which defines the regular intervals, said controlled device selectively operable as a controlled charge-pumping device in a first mode of operation thereof and operable as a controlled current device in a second mode of operation thereof, said controlled device providing a controllable compensating D.C. voltage level shift equal to, and of polarity opposite to, that of the undesired level shift which occurs in one of the regular intervals along the delay line stages.
Claim 7
Dependent Claim
35 words
The charge-transfer delay line circuit set forth in claim 3 wherein said compensating means further comprise means fo controlling the output of said electronically controlled device from a source independent of said delay line stages.
Claim 8
Dependent Claim
34 words
The charge-transfer delay line circuit set forth in claim 4 wherein said compensating means further Comprise means for controlling the output of said current device from a source independent of said delay line stages.
Claim 9
Dependent Claim
35 words
The charge-transfer delay line circuit set forth in claim 5 wherein said compensating means further comprise means for controlling the output of said electronically controlled device from a source independent of said delay line stages.
Claim 10
Dependent Claim
54 words
The charge-transfer delay line circuit set forth in claim 6 wherein said electronically controlled device output controlling means comprises a controlled waveform generator providing a controlled voltage pulse output having a repetition rate greater than the repetition rate of clock pulses supplied to said delay line stages for propagating the sampled analog signal therethrough.
Claim 11
Dependent Claim
53 words
The charge-transfer delay line circuit set forth in claim 7 wherein said current device output controlling means comprises a controlled waveform generator providing a controlled voltage pulse output having a repetition rate greater than the repetition rate of clock pulses supplied to said delay line stages for propagating the sampled analog signal therethrough.
Claim 12
Dependent Claim
54 words
The charge-transfer delay line circuit set forth in claim 8 wherein said electronically controlled device output controlling means comprises a controlled waveform generator providing a controlled voltage pulse output having a repetition rate greater than the repetition rate of clock pulses supplied to said delay line stages for propagating the sampled analog signal therethrough.
Claim 13
Dependent Claim
50 words
The charge-transfer delay line circuit set forth in claim 1 wherein said compensating means comprises at least one controlled semiconductor device operable as a controlled charge-pumping device and having an output connected to an associated at least one selected node along said delay line stages which defines the regular intervals.
Claim 14
Dependent Claim
51 words
The charge-transfer delay line circuit set forth in claim 1 wherein said compensating means comprises at least one controlled semiconductor device operable as a controlled leakage current device and having an output connected to an associated at least one selected node along said delay line stages which defines the regular intervals.
Claim 15
Dependent Claim
71 words
The charge-transfer delay line circuit set forth in claim 1 wherein said compensating means comprises at least one controlled semiconductor device selectively operable as a controlled leakage current device in a first mode of operation and as a controlled charge-pumping device in a second mode of operation thereof and having an output connected to an associated at least one selected node along said delay line stages which defines the regular intervals.
Claim 16
Dependent Claim
165 words
The charge-transfer delay line circuit set forth in claim 14 wherein said plurality of delay line stages comprise a plurality of serially connected field-effect transistor devices of number equal to twice the plurality of delay line stages, and a like plurality of capacitors connected between gate and drain electrodes of corresponding said field-effect transistor devices, the capacitors functioning as temporary charge storage sites for storing the sampled portions of the analog signal applied to the input of said sampling stage, the field-effect transistor devices being sequentially switched to conductive and nonconductive states for propagating the sample analog signal through the delay line stages at the rate at which the transistor devices are switched between states so that the delay line circuit is of the bucket-brigade type, said at least one controlled semiconductor device having an output connected to an associated at least one juncture of selected two of said field-effect transistor devices which defines the at least one selected node along said delay line stages.
Claim 17
Dependent Claim
40 words
The bucket-brigade delay line circuit set forth in claim 15 wherein said controlled semiconductor device is a gate-controlled field-effect type transistor having an interchangeable source or drain electrode connected to the juncTure of the selected two said field-effect transistor devices.
Claim 18
Dependent Claim
20 words
The bucket-brigade delay line circuit set forth in claim 16 wherein said transistors are all of the same field-effect type.
Claim 19
Dependent Claim
65 words
The bucket-brigade delay line circuit set forth in claim 17 wherein said compensating means field-effect transistor has a gate electrode connected to an output of a controlled waveform generator providing a controlled voltage pulse output having a repetition rate greater than the repetition rate of clock pulses supplied to the field-effect transistor devices in the delay line stages for propagating the sampled analog signal therethrough.
Claim 20
Dependent Claim
81 words
The bucket-brigade delay line circuit set forth in claim 18 wherein said compensating means field-effect transistor has an electrode which is the other of the interchangeable source or drain electrode and which is connected to a source of D.C. voltage to thereby cause said compensating field-effect transistor to be operable as a controlled current device to provide a current flow from the compensating node in a direction which is opposite to that resulting from leakage current in the delay line stages.
Claim 21
Dependent Claim
55 words
The bucket-brigade delay line circuit set forth in claim 18 wherein said compensating means field-effect transistor is a metal-oxide-silicon field-effect transistor having an electrode which is the other of the interchangeable source or drain electrode and which is left open to thereby cause said compensating field-effect transistor to be operable as a controlled charge-pumping device.
Claim 22
Dependent Claim
77 words
The bucket-brigade delay line circuit set forth in claim 18 wherein said compensating means field-effect transistor has an electrode which is the other of the interchangeable source or drain electrode and which is connected to ground to thereby cause said compensating field-effect transistor to be operable as a controlled leakage current device wherein the direction of the controlled leakage current being opposite to that resulting from charge pumping or other equivalent phenomenon within the delay line stage.
Claim 23
Dependent Claim
30 words
The charge-transfer delay line circuit set forth in claim 11 wherein said controlled waveform generator is provided with means for adjusting the repetition rate of the voltage pulse output thereof.
Claim 24
Dependent Claim
30 words
The charge-transfer delay line circuit set forth in claim 22 wherein said controlled waveform generator is further provided with means for controlling the amplitude of the voltage pulse output thereof.
Claim 25
Dependent Claim
45 words
The charge-transfer delay line circuit set forth in claim 21 wherein said controlled waveform generator is further provided with means for adjusting the duration of the voltage pulse output thereof, the duration of pulses being in a range up to a 50 percent duty factor.
Claim 26
Dependent Claim
31 words
The charge transfer delay line circuit set forth in claim 11 wherein the frequency of the voltage pulses provided by said controlled waveform generator is approximately 10 times the clock frequency.
Claim 27
Dependent Claim
32 words
The charge-transfer delay line circuit set forth in claim 11 wherein the amplitude of the voltage pulses provided by said controlled waveform generator exceeds the turn-on voltage of said electronically controlled device.
Claim 28
Dependent Claim
41 words
The bucket-brigade delay line circuit set forth in claim 17 and further comprising a switch connected in the other of the interchangeable source or drain electrode circuit of said compensating field-effect type transistor for obtaining the two modes of operation thereof.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |