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Method and means for discriminating between systematic and noise-induced error in data extracted from word organized memory arrays
Assignee: International Business Machines Corp
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Filing: 1977-04-25
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Granted: 1978-07-11
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Expires: 1997-04-25
Abstract
Abstract Systematic and noise-induced errors, as detected in words extracted from corresponding locations in a m × n word organized memory array, are distinguished as to their source and are corrected by using the conjunction of a nonzero error checking syndrome and the a'priori location defects status as indexed by the location address of the extracted words from an external table memory.
Inventors
- 👤 John Scott Eggenberger
- 👤 Arvind Motibhai Patel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
132 words
A method for discriminating between no error, defect induced error, and noise induced error in formatted data normally stored in and extracted from an addressable memory, said data being inclusive of redundancy patterns, the method comprising the steps of: forming a table of concordance between each memory address and its defect status; accessing both formatted data from at least one preselected memory address and the counterpart defect status from the concordance table; determining the syndrome of the accessed data; and indicating from the accessed data the presence of either: a defect induced error upon the concurrence of a non-zero syndrome and a defect at the counterpart memory address; a noise induced error upon the concurrence of a non-zero syndrome and no defect; or no error upon the occurrence of a zero syndrome.
Claim 2
Independent Claim
132 words
A method for discriminating between no error, defect induced error, and noise induced error in formatted data normally stored in and extracted from an addressable memory, said data being inclusive of redundancy patterns, the method comprising the steps of: forming a table of concordance between each memory address and its defect status; accessing both formatted data from at least one preselected memory address and the counterpart defect status from the concordance table; determining the syndrome of the accessed data; and indicating from the accessed data the presence of either: a defect induced error upon the concurrence of a non-zero syndrome and a defect at the counterpart memory address; a noise induced error upon the concurrence of a non-zero syndrome and no defect; or no error upon the occurrence of a zero syndrome.
Claim 3
Independent Claim
198 words
A method for discriminating between no defect, defect induced error, and noise induced error in data formatted as r word tuples of m bits per word and s bits per symbol per word, each r word tuple being normally stored and extracted in a corresponding row of m loops of a m × n array of loops organized as a major/minor loop addressable memory, m bits per word being distributed one to one among the m loops in a row, each word having (m/s)-c data symbols and c checking symbols, the method comprising the steps of: forming a table of concordance between the address of each of n rows of loops and its defect status; accessing an r word tuple from a row of loops and the counterpart defect status from the concordance table; determining the syndrome of the accessed r word tuple; and indicating in the accessed r word tuple, the presence of either: a defect induced error upon the concurrence of a non-zero syndrome and a defect at the counterpart row address; a noise induced error upon the concurrence of a non-zero syndrome and no defect; or no error upon the occurrence of a zero syndrome.
Claim 4
Independent Claim
198 words
A method for discriminating between no defect, defect induced error, and noise induced error in data formatted as r word tuples of m bits per word and s bits per symbol per word, each r word tuple being normally stored and extracted in a corresponding row of m loops of a m × n array of loops organized as a major/minor loop addressable memory, m bits per word being distributed one to one among the m loops in a row, each word having (m/s)-c data symbols and c checking symbols, the method comprising the steps of: forming a table of concordance between the address of each of n rows of loops and its defect status; accessing an r word tuple from a row of loops and the counterpart defect status from the concordance table; determining the syndrome of the accessed r word tuple; and indicating in the accessed r word tuple, the presence of either: a defect induced error upon the concurrence of a non-zero syndrome and a defect at the counterpart row address; a noise induced error upon the concurrence of a non-zero syndrome and no defect; or no error upon the occurrence of a zero syndrome.
Claim 5
Dependent Claim
57 words
A method according to claim 2 wherein the defect status information contained in the table comprises n vectors of m/s positions per vector, a binary indication of a first or second kind in any vector position being respectively indicative of a defect or no defect in a corresponding mutually exclusive pair of adjacent loops in the row.
Claim 6
Dependent Claim
87 words
A method according to claim 2 wherein the memory system of the major/minor loop type comprises a row of m chips, each chip in turn including n parallel loops arranged in a column; the memory system further comprises means for writing bit coded streams into each loop, a mutually exclusive m bit word being formed by each ith bit of each jth loop of each of the m chips; means for recirculating the bit coded streams within the loops; and means for extracting m bit words therefrom.
Claim 7
Dependent Claim
60 words
A method according to claim 4 wherein the memory system extraction means further comprise: m conductors, each conductor coupling the n loops of a corresponding chip; and means for transferring r contiguous bits at a time from each of the n loops to the associated conductor, groupings s of the conductors forming m/s symbol positions in a m bit word.
Claim 8
Dependent Claim
18 words
A method according to claim 2 wherein each symbol consists of sr bits in any r word tuple.
Claim 9
Dependent Claim
33 words
A method according to claim 4, wherein in the memory system two of the m chips are dedicated for storing redundancy bit patterns, wherein m lies in the range 3s≦m≦s (1+2 sr ).
Claim 10
Dependent Claim
20 words
A method according to claim 2 wherein the r word tuple consists of mutually exclusive pairs of contiguously accessible words.
Claim 11
Dependent Claim
41 words
A method according to claim 4 wherein the memory system further comprises a programmable read only memory having n addressable locations for storing m/s bit vector per location, each bit having a first binary value being indicative of a defective chip.
References Cited (Backward Citations)
US3774153A
Cited
USRE28923E
Cited
US3792450A
Cited
US3868632A
Cited
US3909810A
Cited
US4005405A
Cited
US4030067A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-10 | 1982-01-09 | 1982-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-10 | 1986-01-09 | 1986-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-10 | 1990-01-09 | 1990-07-11 | $7700.00 | Window Closed / Lapsed |