Patent US2588742A successfully refreshed from Google Patents.
US4096521A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protective coating for high voltage devices
Assignee: Motorola Solutions Inc
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Filing: 1976-07-08
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Granted: 1978-06-20
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Expires: 1996-07-08
Abstract
Abstract A thermally stable encapsulant for a semiconductor substrate having high voltage devices disposed therein including a coating comprising a polymer having suitable polar characteristics and a metal oxide for depleting excess electron charge and for stablizing ionic contaminants during high voltage operation.
Inventors
- 👤 Keith Gordon Spanjer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:52
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/137; H10W74/111; H10W74/114; H10W74/40; H10W74/47
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
55 words
An encapsulated semiconductor substrate comprising: (a) at least one semiconductor device disposed in said substrate; (b) a coating disposed over said semiconductor device; and (c) said coating comprising a polyimide of the following chemical formulation, ##STR2## and ferric oxide for depleting excess electron charge and for stabilizing ionic contaminants during operation of said semiconductor device.
Claim 2
Dependent Claim
55 words
An encapsulated semiconductor substrate comprising: (a) at least one semiconductor device disposed in said substrate; (b) a coating disposed over said semiconductor device; and (c) said coating comprising a polyimide of the following chemical formulation, ##STR2## and ferric oxide for depleting excess electron charge and for stabilizing ionic contaminants during operation of said semiconductor device.
Claim 3
Dependent Claim
47 words
An encapsulated semiconductor substrate as in claim 1, wherein: (a) said semiconductor device is an NPN transistor, and further comprising; (b) a passivating layer disposed between said coating and said substrate, and said coating depleting excess charge from said passivating layer during operation of said NPN transistor.
References Cited (Backward Citations)
US4024318A
Cited
US3584264A
Cited
US3597269A
Cited
FR2086644A5
Cited
US3939488A
Cited
US3916073A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-19 | 1981-12-19 | 1982-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-19 | 1985-12-19 | 1986-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-19 | 1989-12-19 | 1990-06-20 | $7700.00 | Window Closed / Lapsed |