Memory field effect storage device

Claim 2

An electronic storage device comprising: a p-doped semiconductor substrate having formed therein source and drain regions of n-doped materials, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate member arranged so as to have at least a portion of said insulation layer disposed between said channel and said floating gate and located so as to be able to receive electrons from said channel through said portion of said insulation layer, first means for applying a potential to said source and drain regions to produce a longitudinal field strength and a current of electrons between said source and drain regions, said longitudinal field strength in said carrier channel between said source and drain regions being sufficiently great to accelerate said electrons to a sufficiently great degree that at least a portion of them penetrate said portion of said insulation layer and charge said floating gate by channel injection, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions.

Claim 3

The electronic storage device defined in claim 1 further comprising: a charging gate member, second means for applying a potential to said charging gate of a polarity opposite that of said electrons, the magnitude of said second potential being such, and said charging gate being so located, that said electrons are further accelerated toward said floating gate.

Claim 4

The electronic storage device defined in claim 2 wherein said charging gate is electrically connected to said drain region.

Claim 5

The electronic storage device defined in claim 2 further comprising third means for applying a positive potential to said charging gate for reading the charge state of said floating gate, said third potential being of such a magnitude that said source and drain regions will be conducting if said floating gate is uncharged and will not be conducting if said floating gate is charged.

Claim 6

The electronic storage device defined in claim 2, further comprising fourth potential means connected to said charging gate for applying a potential of a polarity and magnitude to said charging gate which will cause discharge of said floating gate.

Claim 7

The electronic storage device defined in claim 5 wherein said floating gate is discharged by holes generated by avalanche breakdown.

Claim 8

The electronic storage device defined in claim 2 wherein the distance between said charging gate and said floating gate is small relative to the portions of the lengths of said gates which are superimposed over said channel thereby producing capacitive coupling between said two gates.

Claim 9

The electronic storage device defined in claim 2 wherein said charging gate is arranged such that said floating gate is interposed between said charging gate and said carrier channel for controlling the charge and discharge of said floating gate, said floating gate and said charging gate being further arranged and shaped so that the capacitance between said floating gate and said charging gate is greater than the capacitance between said floating gate and said substrate.

Claim 10

The electronic storage device defined in claim 8 wherein said capacitance between said floating gate and said charging gate is substantially formed by an overlap of portions of the latter two gates placed laterally of said source and drain regions.

Claim 11

The electronic stage device defined in claim 2 further comprising: second potential means connected to said charging gate for applying thereto a potential for discharging said floating gate such that electrons stored on said floating gate are accelerated thereby in a direction away from said floating gate into said insulation and through said insulation layer to said channel to one of said source and drain regions.

Claim 12

The electronic storage device defined in claim 10 wherein said electrons are accelerated from said floating gate to the one of said source and drain regions which is fartherest away from the portion of said channel from which electrons are accelerated toward said floating gate during charging.

Claim 13

The electronic storage device defined in claim 10 wherein said second potential is a direct current voltage applied between said charging gate and one of said source or drain regions.

Claim 14

The electronic storage device defined in claim 10 wherein second potential is a train of pulses applied between said charging gate and one of said source or drain regions.

Claim 15

The electronic storage device defined in claim 10 wherein said second potential is formed by a constant potential applied to said charging gate and by pulses applied to said source region.

Claim 16

The electronic storage device defined in claim 14 wherein said floating gate is of a p-doped material such that discharge of said floating gate occurs, at least in part, through heating of electrons stored thereon.

Claim 17

The electronic storage device defined in claim 10 wherein said second potential has a time function as a result of which its amplitude produces a voltage sufficient to cause discharging of said floating gate by the Fowler-Nordheim tunnel effect.

Claim 18

The electronic storage device defined in claim 16 wherein said floating gate is a polycrystalline silicon material.

Claim 19

The electronic storage device defined in claim 16 further comprising: third means for applying a potential between said charging gate and the said region toward which the discharge of said floating gate is to take place, said third potential being of a polarity as to cause said electrons to drift toward the latter region.

Claim 20

The electronic storage device defined in claim 18 wherein said third potential means supplied a sawtooth waveform voltage having a relatively low rise time.

Claim 21

The electronic storage device defined in claim 19 wherein said sawtooth waveform voltage is constituted by a train of amplitude modulated pulses, said pulses being amplitude modulated by said sawtooth waveform voltage.

Claim 22

The electronic storage device defined in claim 10 further comprising means for applying a bias potential to said substrate upon applying said second potential means to said charging gate.

Claim 23

The electronic storage device defined in claim 2 wherein said floating gate is constructed and arranged to be superimposed over only a first portion of said channel, which portion extends through the full width of said channel, and is superimposed over the portion of said channel where said electrons leave said channel to penetrate said insulating layer, said charging gate being constructed and arranged to be superimposed over at least a part of said floating gate and over the remaining portion of said channel, said remaining portion of said channel being connected in series electrically to said first portion of said channel so that the state of the first portion of said channel covered by said floating gate is controlled directly by the state of said charging gate, as well as by the state of said floating gate, but the state of said remaining portion of said channel is controlled directly by said charging gate only.

Claim 24

The electronic storage device defined in claim 22 further comprising: third potential means for applying a potential to said charging gate for charging said floating gate, which potential is positive relative to the potential of said drain region when said channel is in a conducting state.

Claim 25

The electronic storage device defined in claim 22 wherein said floating gate includes a member extending laterally from said channel which forms a conducting connection insulated from said substrate by a thick oxide layer, a portion of said member being insulated from a portion of said source region or said drain region by a thin oxide layer.

Claim 26

The electronic storage device defined in claim 22 wherein said first portion of said channel covered by said floating gate is adjacent to said drain region.

Claim 27

The electronic storage device defined in claim 1 wherein the length of said channel is less than 10 micrometers.

Claim 28

The electronic storage device defined in claim 1 wherein said substrate has specific resistivity greater than 1 ohm-centimeter.

Claim 29

The electronic storage device defined in claim 1 wherein said carrier channel, when said floating gate is uncharged, conducts according to the enhancement mode.

Claim 30

The electronic storage device defined in claim 1 further comprising an additional layer of continuous p-doped material placed on the surface of said p-doped substrate between said drain and source regions and adjacent said insulating layer.

Claim 31

The electronic storage device defined in claim 1 wherein said insulating layer is of a thickness which exceeds the thickness value at which said floating gate, when charged, would be discharged, at least partially, by an avalanche breakdown condition should said drain region be connected to the drain region of another said electronic storage device in which the floating gate therein is being charged.

Claim 32

The electronic storage device defined in claim 30 wherein said thickness value is less than the value at which the quantities of electrons drifting from said floating gate is as large as the quantity of holes flowing under an avalanche breakdown condition from a non-conducting p-n junction of said channel to said floating gate.

Claim 33

Electronic storage apparatus comprising: a plurality of memory cells, wherein each said memory cell comprises one electronic storage device, each said electronic storage device comprising: a p-doped semiconductor substrate having formed therein source and drain regions of n-doped material, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate member arranged so as to have at least a portion of said insulation layer disposed between said channel and said floating gate and located so as to be able to receive electrons from said channel through said portion of said insulation layers, first means for applying a potential to said source and drain regions to produce a longitudinal field strength and a current of electrons between said source and drain regions, said longitudinal field strength in said carrier channel between said source and drain regions being sufficiently great to accelerate said electrons to a sufficiently great degree that at least a portion of them penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions.

Claim 34

Electronic storage apparatus comprising: a plurality of memory cells, wherein each said memory cell comprises one electronic storage device, each said electronic storage device comprising: a p-doped semiconductor substrate having formed therein source and drain regions of n-doped material, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate member arranged so as to have at least a portion of said insulation layer disposed between said channel and said floating gate and located so as to be able to receive electrons from said channel through said portion of said insulation layers, first means for applying a potential to said source and drain regions to produce a longitudinal field strength and a current of electrons between said source and drain regions, said longitudinal field strength in said carrier channel between said source and drain regions being sufficiently great to accelerate said electrons to a sufficiently great degree that at least a portion of them penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions.

Claim 35

The electronic storage apparatus defined in claim 32 wherein said memory cells are arranged in a two dimensional matrix and further comprising: first and second terminals in each electronic storage device connected, respectively, to said source and drain regions and third terminals in said electronic storage devices connected to said charging gates, first control leads connected to said third terminals, second control leads connected to said first terminals and a common terminal connected to said second terminals.

Claim 36

The electronic storage apparatus defined in claim 33 further comprising: first voltage means connected to at least one of said first control leads and to said common terminal for suppying a voltage thereto of a polarity and of sufficient magnitude to discharge said floating gates of connected memory cells, said floating gates thereby being discharged simultaneously.

Claim 37

The electronic storage apparatus defined in claim 33 further comprising: second voltage means connected to said first control leads, said second control leads and said common terminal for applying a potential to said carrier channels of a polarity and magnitude for causing accumulation of negative charges on said floating gates.

Claim 38

An electron storage device comprising: a semiconductor substrate having formed therein source and drain regions of materials producing opposite polarities to that of said substrate, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate member arranged so as to have at least a portion of said insulation layer disposed between said channel and said floating gate and located so as to be able to receive carriers from said channel through said portion of said insulation layer, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain regions, said channel having an inhomogeneity formed therein which, along with the magnitude of said potential, produces a longitudinal field strength between said source and drain regions which is sufficiently great to accelerate said majority carriers to a sufficiently great degree that they penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions.

Claim 39

An electron storage device comprising: a semiconductor substrate having formed therein source and drain regions of materials producing opposite polarities to that of said substrate, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate member arranged so as to have at least a portion of said insulation layer disposed between said channel and said floating gate and located so as to be able to receive carriers from said channel through said portion of said insulation layer, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain regions, said channel having an inhomogeneity formed therein which, along with the magnitude of said potential, produces a longitudinal field strength between said source and drain regions which is sufficiently great to accelerate said majority carriers to a sufficiently great degree that they penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions.

Claim 40

The electron storage device defined in claim 36 further comprising: a charging gate member, second means for applying a potential to said charging gate of a polarity opposite to that of said majority carriers, the magnitude of said second potential being such, and said charging gate being so located, that said majority carriers are further accelerated toward said floating gate.

Claim 41

The electron storage device defined in claim 37 wherein said substrate is a p-doped material, wherein said source and drain regions are n-doped materials and wherein said second potential is positive relative to the potential existing in said channel.

Claim 42

The electron storage device defined in claim 38 further comprising third means for applying a positive potential to said charging gate for reading the charge state of said floating gate, said third potential being of such a magnitude that the source and drain regions will be conducting if said floating gate is uncharged and will not be conducting if said floating gate is charged.

Claim 43

The electron storage device defined in claim 37 wherein said charging gate is electrically connected to said drain.

Claim 44

The electron storage device defined in claim 37 further comprising fourth potential means connected to said charging gate for applying a potential of a polarity and magnitude to said charging gate which will cause discharge of said floating gate.

Claim 45

The electron storage device defined in claim 41 wherein said floating gate is discharged by holes generated by avalanche breakdown.

Claim 46

The electron storage device defined in claim 37 wherein the distance between said charging gate and said floating gate is small relative to the portions of the lengths of said gates which are superimposed over said channel thereby producing a capacitive coupling between said two gates.

Claim 47

The electron storage device defined in claim 36 wherein said substrate is a p-doped material and wherein said source and drain regions are n-doped materials.

Claim 48

The electron storage device defined in claim 44 further comprising an additional layer of continuous p-doped material placed on the surface of said p-doped substrate between said drain and source regions and adjacent said insulating layer.

Claim 49

The electron storage device defined in claim 36 wherein the length of said channel is less than 10 micrometers.

Claim 50

The electron storage device defined in claim 36 wherein said substrate has a specific resistivity greater than 1 ohm-centimeter.

Claim 51

The electron storage device defined in claim 36 wherein said inhomogeneity in said channel is a three dimensional spatial structural inhomogeneity.

Claim 52

The electron storage device defined in claim 36 wherein said channel, when said floating gate is uncharged, conducts according to the enhancement mode.

Claim 53

The electron storage device defined in claim 36 wherein said channel, when said floating gate is uncharged, conducts according to the depletion mode.

Claim 54

The electron storage device defined in claim 36 wherein said inhomogeneity is formed by a narrowing of said channel.

Claim 55

The electron storage device defined in claim 36 wherein said portion of said insulating layer contains a section which is thicker than the remainder of said portion and wherein said inhomogeneity is placed in said channel at a point corresponding to said thicker portion of said insulating layer.

Claim 56

The electron storage device defined in claim 36 wherein said inhomogeneity is placed at one end of said channel.

Claim 57

The electron storage device defined in claim 36 wherein said inhomogeneity is placed substantially at the center of said channel.

Claim 58

The electron storage device defined in claim 36 wherein said inhomogeneity is placed between one end of said channel and the center of said channel.

Claim 59

A field effect transistor storage device comprising: a semiconductor substrate having source and drain regions of a material producing a polarity opposite that of the substrate formed therein, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate arranged so as to have at least a portion of said insulation layer disposed between said channel and said floating gate, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain region, said channel having an inhomogeneity formed therein which, along with the magnitude of said potential, produces a longitudinal field strength between said source and drain regions and accelerates said majority carriers to a sufficiently great degree that they penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions and a charging gate arranged such that said floating gate is interposed between said charging gate and said channel for controlling the charge and discharge of said floating gate, said floating gate and said charging gate being further arranged and shaped so that the capacitance between said floating gate and said charging gate is greater than the capacitance between said floating gate and said substrate.

Claim 60

A field effect transistor storage device comprising: a semiconductor substrate having source and drain regions of a material producing a polarity opposite that of the substrate formed therein, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate arranged so as to have at least a portion of said insulation layer disposed between said channel and said floating gate, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain region, said channel having an inhomogeneity formed therein which, along with the magnitude of said potential, produces a longitudinal field strength between said source and drain regions and accelerates said majority carriers to a sufficiently great degree that they penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions and a charging gate arranged such that said floating gate is interposed between said charging gate and said channel for controlling the charge and discharge of said floating gate, said floating gate and said charging gate being further arranged and shaped so that the capacitance between said floating gate and said charging gate is greater than the capacitance between said floating gate and said substrate.

Claim 61

The field effect transistor storage device defined in claim 56 wherein said capacitance between said floating gate and said charging gate is substantially formed by an overlap portions of the latter two gates placed laterally of said source and drain regions.

Claim 62

The field effect transistor storage device defined in claim 56 further comprising: second potential means connected to said charging gate for applying thereto a potential for discharging said floating gate such that electrons stored on said floating gate are accelerated thereby in a direction away from said floating gate into said insulation layer and through said insulation layer to said channel.

Claim 63

The field effect transistor storage device defined in claim 58 wherein said electrons accelerated from said floating gate to the one of said regions which is fartherest away from the portion of said channel from which electrons are accelerated toward said floating gate during charging.

Claim 64

The field effect transistor storage device defined in claim 58 wherein said second potential is a direct current voltage applied between said charging gate and one of said source and drain regions.

Claim 65

The field effect transistor storage device defined in claim 58 wherein said second potential is a train of pulses applied between said charging gate and one of said source or drain regions.

Claim 66

The field effect transistor storage device defined in claim 58 wherein said second potential is formed by a constant potential applied to said charging gate and by another constant potential applied to said source region.

Claim 67

The field effect transistor storage device defined in claim 58 wherein said second potential is formed by a constant potential applied to said charging gate and by pulses applied to said source region.

Claim 68

The field effect transistor storage device defined in claim 63 wherein said floating gate is of a p-doped material such that discharge of such floating gate occurs at least in part, through heating of electrons stored thereon.

Claim 69

The field effect transistor storage device defined in claim 58 wherein said second potential has a time function, as a result of which its amplitude produces a voltage sufficient to cause discharging of said floating gate by the Fowler-Nordheim tunnel effect.

Claim 70

The field effect transistor storage device defined in claim 65 wherein said floating gate is a p-doped polycrystalline silicon.

Claim 71

The field effect transistor storage device defined in claim 58 further comprising means for applying a bias potential to said substrate upon applying said second potential means to said charging gate.

Claim 72

The field effect transistor storage device defined in claim 58 further comprising: third potential means for applying a potential to said charging gate for charging said floating gate, which potential is positive relative to the potential of said drain region when said channel is in a conducting state.

Claim 73

The field effect transistor storage device defined in claim 56 wherein said insulating layer is of a thickness which exceeds the thickness value at which said floating gate, when charged, would be discharged, at least partially, by an avalanche breakdown condition should said drain region be connected to the drain region of another said field effect transistor storage device in which the floating gate is charged.

Claim 74

The field effect transistor storage device defined in claim 56 wherein said floating gate includes a member extending laterally from said channel which forms a conducting connection insulated from said substrate by a thick oxide layer, a portion of said member covering a portion of said source region or said drain region.

Claim 75

The field effect transistor storage device defined in claim 70 wherein said portion of said channel covered by said floating gate is adjacent to said drain region.

Claim 76

An electronic storage comprising: a plurality of memory cells, each memory cell comprising: a semiconductor substrate having source and drain regions of a material producing a polarity opposite to that of the substrate form therein, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate imbedded in said insulation layer, a controllable charging gate having a first terminal, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain region, said channel having an inhomogeneity formed therein which, along with the magnitude of said first potential, produces a longitudinal field strength between said source and drain regions and accelerates said majority carriers to a sufficiently great degree that they penetrate said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions, second potential means for applying a potential between said charging gate and said main gap for discharging said floating gate by an effect that causes electrons stored on said floating gate to be accelerated in a direction away from said floating gate into said insulation layer and to drift through said insulation layer to said channel, said electronic storage further comprising: first control leads connected to said first terminals, second control leads connected to a one of said regions in each said memory device, said second potential being applied to the one of said first control leads which is connected to the said memory device being discharged and to the said second control lead of that device.

Claim 77

An electronic storage comprising: a plurality of memory cells, each memory cell comprising: a semiconductor substrate having source and drain regions of a material producing a polarity opposite to that of the substrate form therein, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a floating gate imbedded in said insulation layer, a controllable charging gate having a first terminal, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain region, said channel having an inhomogeneity formed therein which, along with the magnitude of said first potential, produces a longitudinal field strength between said source and drain regions and accelerates said majority carriers to a sufficiently great degree that they penetrate said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions, second potential means for applying a potential between said charging gate and said main gap for discharging said floating gate by an effect that causes electrons stored on said floating gate to be accelerated in a direction away from said floating gate into said insulation layer and to drift through said insulation layer to said channel, said electronic storage further comprising: first control leads connected to said first terminals, second control leads connected to a one of said regions in each said memory device, said second potential being applied to the one of said first control leads which is connected to the said memory device being discharged and to the said second control lead of that device.

Claim 78

The electronic storage defined in claim 72 further comprising: third control leads connected to terminals of the others of said regions in said memory devices.

Claim 79

The electronic storage defined in claim 73 further comprising: third potential means for charging said floating gates by being connected to the said first lead of said memory device being charged and fourth potential means for charging said floating gate by connection to ones of said second and third control leads connected to the said memory device being charged.

Claim 80

The n-channel field effect transistor storage device defined in claim 74 wherein said floating gate is superimposed over only a first portion of the width of said channel, said first portion containing the portion of said channel in which said inhomogeneity is located, said charging gate being superimposed over the remaining portion of said channel and being electrically in series so that state of the first portion of said channel is controlled both by the state of said floating gate and by the state of said charging gate, but the state of said remaining portion of said channel is only controlled by the state of said charging gate.

Claim 81

The electronic storage defined in claim 72 further comprising: read potential means for reading said memory devices by connection to a said first control lead of the said memory device being read and read voltage means for reading said memory devices for connection to the ones of said second and third control leads connected to the said memory device being read.

Claim 82

A n-channel field effect transistor storage device comprising: a semiconductor substrate having source and drain regions formed therein of a material producing a polarity opposite to that of the substrate, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a controllable charging gate having a first terminal, a floating gate interposed between said charging gate and said channel and imbedded in said insulation layer, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain region, said channel having an inhomogeneity formed therein which, along with the magnitude of said potential, produces a longitudinal field strength between said source and drain regions and accelerates said majority carriers to a sufficiently great degree that they penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions, second means for applying a potential to said charging gate between said first terminal and said channel for applying a potential of a magnitude and polarity as to cause electrons stored on said floating gate to be accelerated away from said floating gate into a portion of said insulation layer between said floating gate and said channel and to drift through said insulation layer to said channel thereby causing discharge of said floating gate by the Fowler-Nordheim tunnel effect and third means for applying a potential between said first terminal and the said region in said channel toward which the discharge of said floating gate is to take place, said third potential being of a polarity as to cause said electrons to drift toward the latter region.

Claim 83

A n-channel field effect transistor storage device comprising: a semiconductor substrate having source and drain regions formed therein of a material producing a polarity opposite to that of the substrate, another region of said substrate between said source and drain regions forming a carrier channel therebetween, an insulation layer adjacent said substrate, a controllable charging gate having a first terminal, a floating gate interposed between said charging gate and said channel and imbedded in said insulation layer, first means for applying a potential to said source and drain regions to produce a current of carriers having a polarity corresponding to the polarity of the majority carriers in said drain region, said channel having an inhomogeneity formed therein which, along with the magnitude of said potential, produces a longitudinal field strength between said source and drain regions and accelerates said majority carriers to a sufficiently great degree that they penetrate said portion of said insulation layer and charge said floating gate, said floating gate being charged to a sufficiently great degree to inhibit, by electrostatic induction, said majority carrier flow between said source and drain regions, second means for applying a potential to said charging gate between said first terminal and said channel for applying a potential of a magnitude and polarity as to cause electrons stored on said floating gate to be accelerated away from said floating gate into a portion of said insulation layer between said floating gate and said channel and to drift through said insulation layer to said channel thereby causing discharge of said floating gate by the Fowler-Nordheim tunnel effect and third means for applying a potential between said first terminal and the said region in said channel toward which the discharge of said floating gate is to take place, said third potential being of a polarity as to cause said electrons to drift toward the latter region.

Claim 84

The n-channel field effect transistor storage device defined in claim 77 wherein said third potential means supplies a sawtooth waveform voltage having a relatively low rise time.